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Overview
The DesignWare® Ethernet XGXS-PCS core implements the PCS layer of the 10 Gigabit Ethernet Extended Sub-layer (XGXS) as described in the IEEE 802.3ae specification - Clause 47 and Clause 48.
The core is verified using state of the art methodology to reduce the risk of first silicon.
This includes RTL verification, hardware verification and interoperability testing.
Coupled with the DesignWare XAUI-PHY core, the XGXS-PCS provides a complete XGXS solution for quick integration into a SoC design or in a PHY design.
Feature Highlights
- Conversion of dual data rate XGMII to single data rate 312.5MHz data-bus
- Conversion of double data-width (64-bit) XGMII at 156.25 MHz clock to single data rate (32-bit) at 312.5 MHz clock (optional)
- Conversion of XGMII idle control characters to a randomized sequence of code groups to enable lane synchronization, lane-to-lane alignment and clock rate compensation
- 8B/10B encoding/decoding data for each lane
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