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Overview
Synopsys DesignWare Core (DWC) XGMAC core is compliant with the IEEE 802.3ae specification. It interfaces to the PHY layer through the XGMII interface, and to the system through a FIFO interface.
It is a highly configurable and eases SoC integration which allows it to tailor its feature set to the target application.
The XGMAC can be integrated with the DWC XGXS-PCS and the DWC XAUI PHY cores from Synopsys to provide a complete 10 Gigabit Ethernet MAC XAUI solution.
General Features
- Fully compliant IEEE 802.3ae XGMII interface to communicate with an external XGMII PHY
- Supports IEEE 802.3ae Annex 31B flow-control
- Supports VLAN tag processing in compliance with IEEE 802.1Q standard
- IPv4/6 Header Checksum processing for Transmit and Receive
- TCP/UDP/ICMP Checksum insertion and processing for Transmit and Receive
- Complete Network statistics (optional) with RMON/MIB counters (RFC2819/RFC2665)
PHY Interface Features
- Support for XGMII interface at double clock rate or data-width
- Transmit pace rate (programmable) i.e. IPG adjustment to match MAC to PHY rates to SONET /SDH rates
- Local link fault detection and remote fault transmission and detection
System Interface Features
- Native FIFO interface for minimal latency
- Supports 64-bit or 128-bit data interface
- Configurable Big Endian and Little Endian support
Filtering Features
- Up to 32-, 48-bit source and destination address perfect filters with masks for each byte
- 64-, 128-, 256-, 512-bit hash filter (optional) for multicast and uni-cast Destination Addresses (DA)
- VLAN based perfect filter and hash-filter through a 16-bit hash table register
- Flexible options given to filter multicast, uni-cast, broadcast and control frames
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