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Overview
Synopsys DesignWare® DDR2/DDR PHY IP are mixed-signal PHY IP Cores that supply the complete physical interface to JEDEC standard DDR2 and DDR SDRAM Memories. Used together with the DesignWare DDR2/DDR Digital Controller Cores and verification IP, the DDR2/DDR PHYs are the low risk, highest performance, and the only complete, fully validated DDR2/DDR IP solution on the market.
The DesignWare DDR2/DDR PHYs are compiled into a hard macro that is optimized for specific foundry nodes. Each DDR2/DDR PHY is constructed from the following libraries of components: the application specific SSTL I/O library, a master and slave DLL library and Synopsys' unique Interface Timing Module (ITM) library composed of critical controller logic close to the I/Os. The ITMs facilitate the transition from double data rate to single data rate domains and eliminates timing closure issues between RTL-based Controller logic and the hard PHY IP. The DDR2/DDR PHY is assembled by direct cell abutment of the library components that eliminates the need for embedded clock distribution and critical signal timing matching.
The SSTL_18/_2 I/Os featuring programmable drive strength, on-die termination (ODT) and IDDq test mode with LVCMOS input capability provide the JEDEC compliant signaling.
DesignWare DDR2/DDR SDRAM PHYs are compatible with the DesignWare DDR2/DDR Memory Controller IP and the DDR2/3-Lite Protocol Controller IP
Highlights
- When combined with a DesignWare DDR2/DDR digital controller core and verification IP, Synopsys provides a complete DDR2/DDR interface IP solution
- Scalable architecture that supports the full JEDEC speed range, from DDR-250 up to DDR2-1066
- Flexible, hardened macro approach: Three macro libraries are used to build the PHY, the application specific I/Os, Delay Locked Loops (DLLs) and Interface Timing Module (ITM) libraries
- All cells connect by direct abutment resulting in a complete PHY without any routing required - allows maximum flexibility to configure and place according to user requirements (data width, chip constraints, etc.),
while simultaneously taking all the difficult timing closure out of the users hands
- Uses only 4 layers of metal for ITM & DLL
- Uses only 6 layers of metal for I/O cells
- Low latency
- Precision analog DLLs results in ultra low jitter
- Master DLL component for SDRAM command generation and general host timing
- Master/slave DLL component for SDRAM write data generation and read data capture
- Immune to PVT variation
- Uses core voltage level
- Real time DQS drift detection and compensation
- Configurable external data bus widths between 8 and 64 bits in 8-bit increments plus ECC
- Permits operating with DDR/DDR2 SDRAMs using data widths narrower than the compiled data width
- Low area and low power architecture
- Application specific DDR2/DDR I/O library featuring ODT and programmable drive strength (full, half drive) and includes power, analog, spacer, and corner cells.
- Area optimized I/O
- 40um I/O pitch for 130nm and 90nm
- 35um I/O pitch for 65nm
- Staggered I/O supported
- Supports CUP (Circuit Under Pad) and BOA (Bond Over Active)
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