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Overview
The Synopsys DesignWare® DDR2/3-Lite SDRAM Protocol Controller IP Core (PCTL) offers an efficient digital interface between a single on-chip interface and a DDR2 or DDR3 physical layer (PHY) in a DDR2/3 memory subsystem. The DesignWare Protocol Controller provides efficient DDR control and protocol translation without the need of full featured memory controller functions such as multiple application ports, quality of service (QoS) control and optimized memory read/write transaction reordering (often referred to as scheduling).
The PCTL is developed for use with proprietary memory schedulers, enabling the implementation of unique traffic requirements. The PCTL takes a stream of pre-scheduled read and write commands thorough a single application port. It then converts them to DDR protocol and intelligently schedules the precharge, bank activate and refresh commands to optimize the memory channel bandwidth. The PCTL also handles all initialization tasks for the memory subsystem including DRAM initialization and PHY data training. Used together with the DesignWare DDR PHY Cores, the DesignWare DDR2 and DDR2/3-Lite IP solutions are the low risk, highest performance, and most easily integrated DDR2 and DDR2/3 solutions in the market.
The DDR2/3-Lite PCTL is compatible with both the DesignWare DDR2/DDR PHY IP (only supporting DDR2 mode) and the DesignWare DDR2/3-Lite PHY IP.
Highlights
- Supports JEDEC-standard DDR3 and DDR2 protocols (JESD79-3 and JESD79-2, respectively)
- Provides a complete, single vendor DDR3/DDR2 SDRAM interface solution, when combined with the DesignWare DDR2/3-Lite PHY IP
- Provides a complete DDR2 SDRAM interface solution when combined with the DesignWare DDR2/DDR PHY IP (only supports DDR2 mode)
- Contains basic data training logic for supporting DesignWare DDR2/3-Lite and DDR2/DDR PHYs
- Enables automatic translation of application bus reads/writes to bank interleaved DDR3/DDR2 protocol commands (precharge, activate, read, write)
- Schedules out-of-order Activate and Precharge commands to increase memory channel utilization efficiency
- 2:1 architecture (width ratio of 2:1 from application bus to memory data bus) with maximum 533 MHz clock speed for up to 1066Mbps
- Three SDR clock cycles best case latency on the command bus
- Low gate count (40K-80K gates depending on configuration)
- Implements external memory channel width of 8, 16, 32 & 64 bits with no ECC
- With ECC, support for 40 bits (32 bits data, 8 bits for ECC) and 72 bits (64 bits data, 8 bits for ECC)
- Includes software programmable registers to select desired protocol and other controller and PHY configuration
- Supports x8, and x16 memories
- Supports 1 to 4 memory ranks
- Supports up to 32 open memory banks (8 per rank)
- Programmable and flexible open-page, close-page bank management policies
- Bank busy feedback for optimizing external scheduler decision-making
- Automatic power-down entry and exit
- Automatic scheduling of refreshes
- Hardware or software driven self-refresh entry and exit
- Programmable memory initialization to include or exclude DDR3 reset
- Hardware support for full or half width memory data bus, allowing one chip design to support both high performance and low performance systems
- Native application bus interface simplifies memory read/write commands
- APB interface for programming registers
- DDR3 write leveling is not supported in DesignWare DDR2/3-Lite products
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