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Overview
Synopsys DesignWare® DDR2/3-Lite PHY IP solutions are mixed-signal PHY IP Cores that supply the complete physical interface to JEDEC standard DDR3 and DDR2 SDRAM Memories up to 1066Mbps data rates. The DDR2/3-Lite PHY is an area and feature optimized DDR3/2 PHY that is ideal for designers who are currently implementing DDR2 interfaces up to 1066Mbps and want the option of migrating to DDR3 when it becomes more cost effective. As part of the optimization of this PHY, a small number of the new features for DDR3 such as write leveling are not supported as they are not required at 1066Mbps and below.
The DesignWare DDR2/3-Lite PHYs are compiled into a hard macro that is optimized for specific foundry nodes. Each DDR2/3-Lite PHY is constructed from the following libraries of components: the application specific SSTL I/O library, a master and slave DLL library and Synopsys. unique Interface Timing Module (ITM) library. The ITM library is composed of critical controller logic close to the I/Os to facilitate the transition from double data rate to single data rate domains and eliminates timing closure issues between the RTL-based Controller logic and the hard PHY IP. The DDR2/3-Lite PHY is assembled by direct cell abutment of the library components, eliminating the need for embedded clock distribution and critical signal timing matching.
The SSTL_15/_18 I/Os provide fully JEDEC compliant signaling and feature PVT compensated, programmable drive strength, PVT compensated on-die termination (ODT) and IDDq test mode with LVCMOS input capability.
DesignWare DDR2/3-Lite SDRAM PHYs are compatible with the DesignWare DDR2/3-Lite Memory Controller IP and the DDR2/3-Lite Protocol Controller IP.
Highlights
- When combined with a DesignWare DDR2/3-Lite digital controller core and Verification IP Synopsys provides a complete DDR3/2 interface IP solution
- Scalable architecture that supports the full JEDEC speed range, from DDR2-400 up to DDR3-1066
- Flexible, hardened macro approach: Three macro libraries are used to build the PHY, the application specific I/Os, Delay Locked Loops (DLLs) and Interface Timing Module (ITM) libraries
- All cells connect by direct abutment resulting in a complete PHY without any routing required - allows maximum flexibility to configure and place according to user requirements (data width, chip constraints, etc.), while simultaneously taking all the difficult timing closure out of the users hands
- Uses only 4 layers of metal for ITM & DLL
- Uses only 6 layers of metal for I/O cells
- Low latency
- Precision analog DLLs results in ultra low jitter
- Master DLL component for SDRAM command generation and general host timing
- Master/slave DLL component for SDRAM write data generation and read data capture
- Immune to PVT variation
- Uses core voltage level
- Real time DQS drift detection and compensation
- Configurable external data bus widths between 8 and 64 bits in 8-bit increments plus ECC
- Permits operating with DDR3/2 SDRAMs using data widths narrower than the compiled data width
- Low area and low power architecture
- Area optimized I/O: 35um I/O pitch
- Application specific DDR3/2 I/O library featuring PVT independent ZQ/RZQ programmable ODT and drive strength
- Includes RTL controller logic for calibration
- Includes power, spacer, and corner cells
- Supports CUP (Circuit Under Pad)
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