HELPING YOU DESIGN THE CHIP INSIDE
Products and Solutions
---------- SOLUTIONS ----------
Eclypse Low Power Solution
Galaxy Design Platform
Design for Low Power
Design for Test
Design for Yield
RTL Synthesis
Physical Implementation
Sign-Off
Liberty CCS
SDC
Milkyway
Discovery Verification Platform
Analysis and Debug Tools
Low-Power Verification
System Analysis & Design
Smart RTL Verification
Functional Equivalence Checking
Mixed-Signal
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DesignWare Library
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DesignWare Cores
DesignWare Star IP
DesignWare Foundry Libraries
IP Reuse Tools
Design for Manufacturing
Design-Yield Analysis
Mask Synthesis
Mask Data Preparation
Lithography Verification
TCAD
Manufacturing Yield Management
Professional Services
Tool and Methodology Deployment
Pilot Design Environment
Flow Optimization
Implementation
Verification Consulting
Concept to Parts
Core Hardening
---------- PRODUCTS ----------
BSD Compiler: Test synthesis
Cadabra: Cell creation
Calibration Library
CATS: Mask data preparation
Circuit Explorer: Analysis & Optimization
coreAssembler
coreBuilder
coreConsultant
CosmosLE: Layout design environment
CosmosScope: Waveform analysis
CosmosSE: Schem. design environment
DC Ultra: RTL synthesis
Design Analyzer: RTL synthesis
Design Compiler: RTL synthesis
DesignWare: Design & verif. IP
DesignWare Virtual Platforms
DFT Compiler MAX
DFT Compiler: Test synthesis
DSSA Sentry
Enterprise: Layout editor
ESP: Transistor-level Equivalence Checking
Formality: Funct. equiv. checking
Hercules: Physical verification
HSIM
HSPICE: Accurate circuit simulation
IC Compiler
IC Workbench
Innovator: SoC / system modeling
JupiterXT: Design planning
Leda: RTL checker
Library Compiler: Library compilation
Liberty NCX: CCS Characterization
Magellan: RTL formal verification
Memory Solution
Milkyway: Design database
MVRC
MVSIM
NanoChar: 90 nanometer & below characterization
NanoSim: Fast circuit simulation
NanoTime
Odyssey Defect/Odyssey YMS
Paramos
Pilot Design Environment
Pioneer-NTB: SystemVerilog testbench automation
Power Compiler: Power optimization
PrimePower: Power analysis
PrimeRail
PrimeTime PX
PrimeTime: Static timing analysis
PrimeTime SI: Signal integrity analysis
PrimeYield Tool Suite
Proteus OPC
PSM-Create & PSM-Check
Raphael
Raphael NXT
Recipe Manager and Editor (RME)
Saber: Multi-tech. simulation
Scirocco: VHDL simulation
Seismos
Sentaurus Device
Sentaurus Lithography
Sentaurus Process
Sentaurus Structure Editor
Sentaurus TFM
Sentaurus Topography
Sentaurus Workbench
SiVL-LRC: Lithography verification
SpiceCheck
SpiceExplorer
Star-RCXT: Full-chip RC extraction
Star-RCXT VX
Star-SimXT: Fast circuit simulation
System Studio: DSP algorithm design
Taurus-Medici
Taurus-TSuprem4
TestChip Products
TetraMAX: ATPG
VCS: Comprehensive RTL Verification
VCS MX: Mixed-HDL simulation
Vera: Testbench automation
WaveView Analyzer
DESIGN IMPLEMENTATION
VERIFICATION
INTELLECTUAL PROPERTY
DFM/TCAD
DESIGN SERVICES
ADDITIONAL RESOURCES
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DesignWare® Articles
Low Power Design for Analog/Mixed-Signal IP
(Mar 2008)
Designers Highlight Challenges of High-Speed I/O
(Nov 2007)
Certified Wireless USB and Ultra-wideband to the Rescue
(Aug 2007)
EETimes: Letter to the Editor: Synopsys Weighs In
(Aug 2007)
EETimes: Analog and Mixed-Signal Connectivity IP at 65nm and Below
(May 2007)
ChipDesign Trends: Synopsys Prepares for Future Growth in IP Segment
(Mar 2007)
DesignCon panel: 65-nm technology ready for mixed-signal designs; analog ICs, not so much
(Jan 2007)
ChipDesign Trends: Analog IP -- Ready for Prime Time?
(Feb 2007)
SOCcentral: Building a Total Quality Experience into Silicon IP
(Aug 2006)
ENews: What.s Right and Wrong with IP?
(Aug 2006)
ENews: IP Reuse Can Usher in a Renaissance
(Mar 2005)
New Electronics: Revolutionary IP
(Jan 2005)
ENews: Intellectual Quandary
(Jan 2005)
EE Design: How to select verification IP
(Dec 2004)
ENews: Intellectual Discussion
(Dec 2004)
EETimes: 8-bit microcontrollers: still going . . .
(Dec 2004)
Compiler: Accessing TSMC Libraries Through DesignWare Library
(Dec 2004)
ENews: VIP: It's Time to Grow Up
(Sep 2004)
ENews: Synopsys' PCI Express Core Gets Nod From PCI-SIG
(Aug 2004)
Compiler: Collaboration Makes New Commercial Ultra Low-Power Solution Accessible To Designers
(Aug 04)
DSP Engineering: Today's DSP design challenge - power efficiency
(Jul 2004)
ENews: Chief IP Office Wanted - Roundtable with Ed Sperling
(Jul 2004)
EETimes: Delivering verified AMBA AXI systems-on-chips
(Jul 2004)
Compiler Magazine: IP = Verification? - Part 2
(May 2004)
EETimes: Synopsys adds Philips' CoolFlux DSP to DesignWare library
(May 2004)
Compiler Magazine: IP = Verification? - Part 1
(Mar 2004)
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