| High performance, low latency interconnect fabric for AMBA 3 AXI (DW_axi) |
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- Multiple address multiple data architecture for maximum bandwidth utilization.
- Advanced internal pipelining options, up to 2 separate pipeline stages per channel for high frequency operation.
- Master/Slave visibility to reduce area and increase performance.
- Range of arbitration options for each channel, from priority based arbitration to fair arbitration schemes.
- Full ID ordering model support. Multiple outstanding transactions with different ID's from each master.
- Support for write data from different masters to be interleaved to slaves.
- Bi-Directional command support for multi-interconnected subsystems
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| High performance, low latency interconnect fabric and bridge for AMBA 2 & 3 APB for direct connect to AMBA 3 AXI fabric (DW_axi_x2p) |
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- Provides full APB master functionality, APB slave decoding and multiplexing.
- Configurable buffer depths for bus offloading.
- Performs data consistency checking, with AXI error generation.
- Downsizes larger AXI data beats to smaller APB data busses.
- Supports both AMBA 2.0 and 3.0 APB slaves.
- Comprehensive clocking options with configurable synchronization depths.
- Configurable data endianness translation.
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| Configurable standalone pipelining stage for AMBA 3 AXI subsystems (DW_axi_rs) |
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- Provides timing isolation on any AXI connection with no throughput penalty.
- User configurable to pipeline forward, backward or all channel paths.
- Flexibility to pipeline only the desired AXI channels
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| High performance, low latency interconnect fabric for AMBA 2 AHB (DW_ahb) |
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- Full protocol support, split, retry, early burst termination and more.
- Advanced programmable arbitration options. From priority based to fair arbitration to guaranteed QOS (weighted token).
- Configurable system endianness, static or dynamically controlled.
- Support for memory remap and contiguous or non-contiguous slave memory regions.
- Configurable support for undefined length bursts or undefined length burst termination.
- Additional AMBA-lite mode optimizes fabric for single master systems
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| Configurable multi-layer interconnection matrix (DW_ahb_icm) |
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- Allows up to 8 AHB layers to access a common AHB slave.
- Full protocol support, split capable slave, AHB locking and more.
- Starvation prevention features, RETRY issued to layers waiting longer than a configured time limit.
- Static layer arbitration scheme. External layer priorities supported.
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| High performance, low latency interconnect fabric & bridge for AMBA 2 APB for direct connect to AMBA 2 AHB fabric (DW_apb) |
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- Supports up to 16 APB slaves.
- Matches a larger AHB data width to a smaller APB data width.
- Supports an AHB clock with is an integer multiple of the APB clock.
- Configurable support for an external decoder.
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| Bridge from AMBA 3 AXI to AMBA 2.0 AHB, enabling easy integration of legacy AHB designs with newer AXI systems (DW_axi_x2h) |
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- Large range of configurable buffer depths for bus offloading.
- Supports data downsizing from a larger AXI bus to a smaller AHB bus.
- Configurable clock domain crossing, optimized for asynchronous, synchronous or single clock operation.
- Provides pipelining options to for high frequency operation.
- Additional AHB-lite mode enables optimizations for single master AHB subsystems.
- Configurable data endianness translation
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| Flexible bridge between multiple AMBA 3 AXI components or busses (DW_axi_x2x) |
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- Large range of configurable buffer depths for bus offloading.
- Data widths of up to 512 on either interface with full translation between them.
- Option to perform data upsizing going from a smaller to larger data width.
- Low latency operation with pipelining options for high performance.
- Comprehensive clocking options with configurable synchronization depths.
- Full ID ordering model support, with both read and write interleaving and reordering supported at both interfaces.
- Configurable number of multiple outstanding transactions
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| Configurable high performance interface from and AHB master to an AXI slave (DW_axi_hmx) |
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- Buffered writes for high performance.
- Static or dynamic transaction blocking for transaction ordering enforcement.
- Configurable AHB to AXI endianness conversion.
- Support for slower synchronous AHB clock.
- Multiple pipelining options for high frequency operation.
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| Area efficient, low bandwidth AMBA 2 AHB to AHB Bridge (DW_ahb_h2h) |
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- Performs data bus downsizing.
- Comprehensive clocking options and clock domain crossing for both synchronous and asynchronous clocks.
- Very low gate count implementation, as low as 2K for a minimum configuration.
- Configurable data endianness translation.
- Additional AHB-lite mode enables optimizations for single master systems.
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| High performance, high bandwidth AMBA 2 AHB to AHB bridge (DW_ahb_eh2h) |
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- Large range of channel buffer depths for bus offloading.
- Statically or dynamically controllable split generation from the slave interface to free bus cycles until resources available.
- Pre-fetched read data, returned on split completion.
- Asynchronous or synchronous clocks on both interfaces.
- Posted writes with interrupt generation on write error responses.
- Pipelining options for high frequency performance
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| Simplify the connection of third party/custom master controllers to the AMBA 3 AXI fabric (DW_axi_gm) |
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- Translates from a generic request and response channel to the 5 channel AXI interface.
- Low latency operation with 100% throughput efficiency.
- Provides pipelining options to ease timing closure.
- Configurable to allow transactions to be blocking or non-blocking.
- Support for different synchronous clocks on each interface.
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| Simplify the connection of third party/custom slave controllers to the AMBA 3 AXI fabric (DW_axi_gs) |
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- Low latency operation with 100% throughput efficiency.
- Provides pipelining options to ease timing closure.
- Generic interface lite mode to interface with simple slaves e.g. an SRAM.
- Ability to monitor multiple AXI exclusive accesses.
- Support for different synchronous clocks on each interface
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| Configurable vectored interrupt controllers for AHB or APB bus systems (DW_ahb_ictl / DW_apb_ictl) |
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- Separate peripherals, 1 with an AHB slave interface, 1 with an APB slave interface.
- Up to 64 normal interrupt sources, and 8 fast interrupt sources.
- Combinatorial interrupt processing, interrupts propagate without clock running.
- Interrupts can be enabled, masked, forced (software interrupts) and software sampled at all stages.
- Priority based interrupt filtering, with support for programmable interrupt source priorities.
- Vectored interrupt generation.
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| Verification IP for AMBA 2 AHB/APB and AMBA 3 AXI |
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- SystemVerilog, VHDL and OpenVera testbenches to generate bus traffic and check for protocol violations. Monitors provide extensive reports to show functional coverage of the bus protocols.
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