Compute Platforms:
Want to know if your hardware and operating system will support Synopsys EDA software? Visit the Synopsys Compute Platforms website to find out.
Libraries:
Access to libraries that can be used in teaching and research is often difficult to find. We have provided a list of available library references for you here. As a reminder, if you intend to take your design to silicon you should obtain access to a commercial library from MOSIS or other authorized IC fabrication services.
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| | | IPL Library
A proof of concept Interoperable PCell library from the IPL Alliance. The IPL (Interoperable PDK Libraries) Alliance is an industry wide collaborative effort to create and promote interoperable process design kit (PDK) standards.
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| | | Free PDK
FreePDK is an effort to develop an open-source, Open-Access-based PDK for the 45nm technology node and the Predictive Technology Model.
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| | | Free 45nm Open Source Digital Cell Library
Provided by Nangate this library includes: several new user-requested cell variants, CCS and ECSM timing models as well as a DFM kit for yield sensitivity analysis.
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| | | Scalable CMOS Library
Technologies supported: AMI 0.5um (with pad cells), AMI 0.35um (with pad cells), TSMC 0.25um, TSMC 0.18um
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| | | 90nm Generic Library - coming soon!
Provided by Synopsys this library includes: technology kit, digital standard cell library, I/O standard cell library, set of memories and phase locked loop. It will be made available to Synopsys University Program members.
If you are interested in beta testing this library with your Synopsys tool set please contact us.
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Processors:
The following processors are available free of charge for academic use.
FPGA Products:
Synopsys recommends the following Synplicity FPGA products.
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| | | Product: Synplify Pro
The industry's most widely used FPGA synthesis solution, Synplify Pro uses a true timing-driven approach to synthesis. Synplify Pro software delivers the performance you need to meet your design's timing requirements and then optimizes your circuit for area, saving significantly on chip cost.
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| | | Product: Synplify Premier
The Synplify Premier solution builds upon Synplicity's industry-leading synthesis technology and adds new graph-based physical synthesis and real-time, simulator-like visibility into operating FPGA devices. Graph-based physical synthesis provides rapid timing closure and up to a 5-20% timing improvement.
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| | | Product: Synplify DSP
The Synplify DSP tool provides a unique ESL synthesis methodology that realizes significant productivity and portability advantages over traditional HDL design flows. System and algorithm designers can quickly capture complex algorithmic behavior using the Synplify DSP library, which includes powerful modeling features such as vector arithmetic, fixed-point precision up to 128-bits, and a rich set of IP cores.
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| | | Product: Identify
Identify RTL Debugger is the first software tool that allows you to probe and debug your FPGA design directly in the source RTL. You use Identify software to verify your design in hardware as you would in simulation – only much faster and with in-system stimulus. The Identify tool allows you to navigate your design graphically and mark signals directly in RTL as probes or sample triggers. After synthesis, you view the results in the RTL source code or in waveform. Design iterations are rapidly done using incremental place and route. Identify software is closely integrated with synthesis and routing tools for a seamless development environment.
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| | | Product: Certify
Certify® ASIC prototyping solution is the leading product for ASIC prototyping using multiple FPGAs. Certify software combines RTL multi-chip partitioning with best-in-class FPGA synthesis. Using the Certify product makes ASIC prototyping significantly easier, shortens prototype development time, improves prototype performance, and enables faster time-to-market.
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For more information about the Synplicity University Program please visit the website or contact the Synplicity University Program team.
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