HELPING YOU DESIGN THE CHIP INSIDE Products and Solutions ---------- SOLUTIONS ---------- Eclypse Low Power Solution Galaxy Design Platform • Design for Low Power • Design for Test • Design for Yield • RTL Synthesis • Physical Implementation • Sign-Off • Liberty CCS • SDC • Milkyway Discovery Verification Platform • Analysis and Debug Tools • Low-Power Verification • System Analysis & Design • Smart RTL Verification • Functional Equivalence Checking • Mixed-Signal • Languages Intellectual Property (IP) • DesignWare Library • DesignWare Verification IP • DesignWare Cores • DesignWare Star IP • DesignWare Foundry Libraries • IP Reuse Tools Design for Manufacturing • Design-Yield Analysis • Mask Synthesis • Mask Data Preparation • Lithography Verification • TCAD • Manufacturing Yield Management Professional Services • Tool and Methodology Deployment • Pilot Design Environment • Flow Optimization • Implementation • Verification Consulting • Concept to Parts • Core Hardening ---------- PRODUCTS ---------- BSD Compiler: Test synthesis Cadabra: Cell creation Calibration Library CATS: Mask data preparation Circuit Explorer: Analysis & Optimization coreAssembler coreBuilder coreConsultant CosmosLE: Layout design environment CosmosScope: Waveform analysis CosmosSE: Schem. design environment DC Ultra: RTL synthesis Design Analyzer: RTL synthesis Design Compiler: RTL synthesis DesignWare: Design & verif. IP DesignWare Virtual Platforms DFT Compiler MAX DFT Compiler: Test synthesis DSSA Sentry Enterprise: Layout editor ESP: Transistor-level Equivalence Checking Formality: Funct. equiv. checking Hercules: Physical verification HSIM HSPICE: Accurate circuit simulation IC Compiler IC Workbench Innovator: SoC / system modeling JupiterXT: Design planning Leda: RTL checker Library Compiler: Library compilation Liberty NCX: CCS Characterization Magellan: RTL formal verification Memory Solution Milkyway: Design database MVRC MVSIM NanoChar: 90 nanometer & below characterization NanoSim: Fast circuit simulation NanoTime Odyssey Defect/Odyssey YMS Paramos Pilot Design Environment Pioneer-NTB: SystemVerilog testbench automation Power Compiler: Power optimization PrimePower: Power analysis PrimeRail PrimeTime PX PrimeTime: Static timing analysis PrimeTime SI: Signal integrity analysis PrimeYield Tool Suite Proteus OPC PSM-Create & PSM-Check Raphael Raphael NXT Recipe Manager and Editor (RME) Saber: Multi-tech. simulation Scirocco: VHDL simulation Seismos Sentaurus Device Sentaurus Lithography Sentaurus Process Sentaurus Structure Editor Sentaurus TFM Sentaurus Topography Sentaurus Workbench SiVL-LRC: Lithography verification SpiceCheck SpiceExplorer Star-RCXT: Full-chip RC extraction Star-RCXT VX Star-SimXT: Fast circuit simulation System Studio: DSP algorithm design Taurus-Medici Taurus-TSuprem4 TestChip Products TetraMAX: ATPG VCS: Comprehensive RTL Verification VCS MX: Mixed-HDL simulation Vera: Testbench automation WaveView Analyzer DESIGN IMPLEMENTATION VERIFICATION INTELLECTUAL PROPERTY DFM/TCAD DESIGN SERVICES TSMC SOLUTIONS PRESS RELEASES RELATED LINKS Strategic Alliances Universities Interoperability TSMC.com TSMC DFM Utilities Download Press Releases 06/11/08 Synopsys Honors IPL Alliance Companies With Eighth Annual Tenzing Norgay Interoperability Achievement Award 06/04/08 Synopsys Delivers Comprehensive Design Support for TSMC 40-Nanometer Process 05/14/08 Synopsys and TSMC Collaborate on Advanced HSPICE Modeling Technology for 40-nm Processes 03/17/08 Synopsys IC Compiler Routing Qualifies for TSMC's 45-Nanometer Process 12/11/07 Synopsys, Altera and TSMC Collaboration Delivers Industry-Leading 45-Nanometer Extraction Accuracy 11/13/07 Synopsys Implements New High-Speed, Design-to-Mask Data Processing Software for TSMC Advanced Process Technologies 06/04/07 Synopsys Announces Advanced Techniques In TSMC Reference Flow 8.0 to Address 45nm Design Challenges 05/15/07 Synopsys Unveils Industry's First Certified Hi-Speed USB 'On-the-Go' nanoPHY IP for TSMC'S 65-Nanometer Process 03/06/07 TSMC and Synopsys Announce CCS Model Support for TSMC'S 65-Nanometer Process 07/18/06 TSMC Reference Flow 7.0 Incorporates Synopsys' IC Compiler 07/17/06 TSMC Bolsters Design Ecosystem with DFM-Compliant EDA Tools and Data Kit for 65nm Design 07/17/06 TSMC Continues Industry Leadership with Reference Flow 7.0 06/28/06 Synopsys Introduces Validated USB 2.0 nanoPHY IP for TSMC'S NexsysSM 90-LP Process 05/17/06 TSMC Names Synopsys to Distribute Its Production-Ready 65-nm Nexsys Libraries 05/17/06 Synopsys Partners with TSMC to Offer Comprehensive DFM Solution for Yield Enhancement 12/07/05 Synopsys Offers First Certified TSMC 90-Nanometer USB 2.0 OTG PHY IP 10/24/05 TSMC Adopts Synopsys TetraMAX for Yield Diagnostics 06/21/05 TSMC, NVIDIA and VLSI Research to Keynote at 11th Annual Advanced Reticle Symposium 06/09/05 Key Synopsys Low Power and DFM Technologies Support TSMC Reference Flow 6.0 CONTACT US  | FEEDBACK  | LOCATIONS  |  PRIVACY POLICY  |  LEGAL

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