| |||||||||||||||||||||||||||||||
|
The V-SDC format contains information to streamline functional verification through the use of equivalence checking. The V-SDC format provides a record of changes that occur during design implementation. Downstream tools can use this information to improve design understanding and provide faster time to results. As an example, during synthesis a register might be duplicated to improve drive strength. In the past, equivalence checking tools required user-specified setup information to account for this difference. Today, V-SDC can be used as the automated mechanism to understand these types of design optimizations. V-SDC User Guide The User Guide is free-of-charge and available for download on the TAP-in web site. Interoperability Developers' Forum All licensees of V-SDC automatically become part of the Developers' Forum. The Developers' Forum is designed to provide licensees with information and support to incorporate V-SDC into their tools and design flows. The forum is geared towards technical developers of EDA tools. During the Developers' Forum, which is usually held biannually, licensees learn about future plans for V-SDC, obtain updated documentation, become familiar with support channels, find out about scheduled training and other events, plus share experiences with each other. See the events section for more information on the next Developers' Forum. How To Become a V-SDC Licensee The open source license for V-SDC is free and available now. To download, Register now! to receive your password and login codes. For additional information regarding V-SDC or the TAP-in Program, please contact us at: tap-in@synopsys.com |
||||||||||||||||||||||||||||||
|
|||||||||||||||||||||||||||||||
