HELPING YOU DESIGN THE CHIP INSIDE
Products and Solutions
---------- SOLUTIONS ----------
Eclypse Low Power Solution
Galaxy Design Platform
• Design for Low Power
• Design for Test
• Design for Yield
• RTL Synthesis
• Physical Implementation
• Sign-Off
• Liberty CCS
• SDC
• Milkyway
Discovery Verification Platform
• Analysis and Debug Tools
• Low-Power Verification
• System Analysis & Design
• Smart RTL Verification
• Functional Equivalence Checking
• Mixed-Signal
• Languages
Intellectual Property (IP)
• DesignWare Library
• DesignWare Verification IP
• DesignWare Cores
• DesignWare Star IP
• DesignWare Foundry Libraries
• IP Reuse Tools
Design for Manufacturing
• Design-Yield Analysis
• Mask Synthesis
• Mask Data Preparation
• Lithography Verification
• TCAD
• Manufacturing Yield Management
Professional Services
• Tool and Methodology Deployment
• Pilot Design Environment
• Flow Optimization
• Implementation
• Verification Consulting
• Concept to Parts
• Core Hardening
---------- PRODUCTS ----------
BSD Compiler: Test synthesis
Cadabra: Cell creation
Calibration Library
CATS: Mask data preparation
Circuit Explorer: Analysis & Optimization
coreAssembler
coreBuilder
coreConsultant
CosmosLE: Layout design environment
CosmosScope: Waveform analysis
CosmosSE: Schem. design environment
DC Ultra: RTL synthesis
Design Analyzer: RTL synthesis
Design Compiler: RTL synthesis
DesignWare: Design & verif. IP
DesignWare Virtual Platforms
DFT Compiler MAX
DFT Compiler: Test synthesis
DSSA Sentry
Enterprise: Layout editor
ESP: Transistor-level Equivalence Checking
Formality: Funct. equiv. checking
Hercules: Physical verification
HSIM
HSPICE: Accurate circuit simulation
IC Compiler
IC Workbench
Innovator: SoC / system modeling
JupiterXT: Design planning
Leda: RTL checker
Library Compiler: Library compilation
Liberty NCX: CCS Characterization
Magellan: RTL formal verification
Memory Solution
Milkyway: Design database
MVRC
MVSIM
NanoChar: 90 nanometer & below characterization
NanoSim: Fast circuit simulation
NanoTime
Odyssey Defect/Odyssey YMS
Paramos
Pilot Design Environment
Pioneer-NTB: SystemVerilog testbench automation
Power Compiler: Power optimization
PrimePower: Power analysis
PrimeRail
PrimeTime PX
PrimeTime: Static timing analysis
PrimeTime SI: Signal integrity analysis
PrimeYield Tool Suite
Proteus OPC
PSM-Create & PSM-Check
Raphael
Raphael NXT
Recipe Manager and Editor (RME)
Saber: Multi-tech. simulation
Scirocco: VHDL simulation
Seismos
Sentaurus Device
Sentaurus Lithography
Sentaurus Process
Sentaurus Structure Editor
Sentaurus TFM
Sentaurus Topography
Sentaurus Workbench
SiVL-LRC: Lithography verification
SpiceCheck
SpiceExplorer
Star-RCXT: Full-chip RC extraction
Star-RCXT VX
Star-SimXT: Fast circuit simulation
System Studio: DSP algorithm design
Taurus-Medici
Taurus-TSuprem4
TetraMAX: ATPG
VCS: Comprehensive RTL Verification
VCS MX: Mixed-HDL simulation
Vera: Testbench automation
WaveView Analyzer
DESIGN IMPLEMENTATION
VERIFICATION
INTELLECTUAL PROPERTY
DFM/TCAD
DESIGN SERVICES
WHAT'S NEW: TAP-in
TAP-in NEWS
TAP-in EVENTS
TAP-in ARTICLES
OPEN SOURCE COMMENTS
CONTACT TAP-in
EDA Interoperability Developers' Forum
Presentations from April 2004
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General Session
Galaxy Design Platform Interoperability via Milkyway C-API
Mark Lefevre, Synopsys
Milkyway Session
Achieving Interoperability with the Milkyway API
John McGehee, Voom, Inc.
The GoldenGate Working Group Update
Jim Wilmore, HP
Application for Hierarchy Walker
Tina Nguyen, Synopsys
Tcl Shell for Milkyway
Noel Strader, Synopsys
MAP-in R&D Update
James Hseuh, Synopsys
Closing Remarks
Rich Goldman, Synopsys
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© 2008 Synopsys, Inc. All Rights Reserved.
