|
What SystemVerilog Catalyst Partners are Saying
- Alatek
- “Alatek welcomes the industry adoption of the powerful SystemVerilog language. We are confident that SystemVerilog is the new innovation in SoC design. This is why we have put all our efforts into providing hardware accelerators and emulators that will work seamlessly with SystemVerilog. We believe that the combined performance of hardware and software solutions supporting SystemVerilog will help make it a universal design platform.”
Stanley Hyduke, founder, president and CEO, Alatek, Inc.
- Aldec
- “We at Aldec have been excited with the new features of the SystemVerilog language and are in the process of implementing them in our Riviera mixed-HDL simulator. Our customers will be able to add assertions and synthesizable constructs in the beginning of 2004. We also see a big interest in high-level testbench features and integration with the C++ language for SoC designs. These constructs will be added in subsequent releases of our simulator.”
Gregor Siwinski, Director of R&D, Aldec.
- Aptix
- “SystemVerilog lays the foundation for major advancements in design and verification products and methodologies. Through SystemVerilog language support, Aptix can boost its prototyping flow to higher levels of abstraction using transaction level co-emulation. With synthesizable assertions, we can now conduct even smarter RTL verification by supplying error information to workstation during co-emulation or in-circuit operation. This works at either the cycle level or transaction level of verification.”
Dr. Amr Mohsen, founder, chairman and CEO, Aptix Corporation
- ARM
- “ARM welcomes this move by Synopsys to make its SystemVerilog-based tools more open and accessible to the design community. ARM is actively working with Synopsys to ensure that our IP is well placed to support our Partners who wish to take advantage of the benefits offered by this important new language.”
Simon Segars, executive vice president of engineering, ARM.
- Atrenta
- “Atrenta sees SystemVerilog as the next frontier in high level design and verification for SoCs. We are pleased to work with Synopsys and accelerate the adoption of the language by supporting it in our SpyGlass Predictive Analysis suite of tools.”
Dr. Ajoy Bose, chairman, president and CEO, Atrenta.
- Avery Design Systems
- “SystemVerilog lays the groundwork for the next wave of breakthroughs in design and verification tools and methods. SystemVerilog is central to Avery Design's delivering on our auto-directed functional testing (ADFT) strategy that enables engineers to comprehensively verify hard to reach deep functional corner cases in less time and effort.”
Chris Browy, vice president of sales and marketing, Avery Design Systems.
- Beach Solutions
- “In order for today's complex System-on-Chip designs to be successful, an effective design re-use strategy is essential. Beach Solutions' tools facilitate the easy adoption of design re-use strategies within existing design flows. This applies equally to IP for hardware design, software design and test. We are, therefore, pleased to be partnering with Synopsys in the promotion of SystemVerilog through their Catalyst program. Adding SystemVerilog to our automated generators will significantly enhance the range of design flows we can support.”
Terry McCloskey, CEO, Beach Solutions.
- Bluespec
- “SystemVerilog is the only language choice that allows the majority of hardware designers to raise the level of abstraction in describing hardware and simultaneously produce a synthesizable specification.The cooperative work of the Accellera standards group is further enhanced by Synopsys' SystemVerilog Catalyst program in ensuring interoperability among the tools.”
Shiv Tasker, CEO, Bluespec, Inc.
- ChipVision
- “Since it combines the best of hardware design and verification languages, SystemVerilog enables users to create unified environments for developing designs, assertions and testbenches. ChipVision is excited to join the SystemVerilog Catalyst program to ensure interoperability. This program not only accelerates vendor support, it also hastens widespread adoption of this important new language. In 2004, ChipVision plans to provide SystemVerilog output support in ORINOCO, our system-level power analysis and optimization tool.”
Joachim Riewesell, chief marketing officer, ChipVision.
- Doulos
- “The advent of SystemVerilog provides an opportunity for designers to achieve better productivity with a better Verilog. As part of its longstanding commitment to the large Verilog community, Doulos will bring its independent training expertise to bear to enable a rapid move up that productivity curve.”
Rob Hurley, managing director, Doulos.
- EVE
- “The SystemVerilog language lets our customers design within one consistent Verilog environment to improve functional coverage and transaction-based stimuli generation. With the synthesizable portions of their design transparently mapped inside our hardware emulator and the sophisticated testbench taking advantage of the new extensions of the language, our customers will boost their productivity by a few orders of magnitude.”
Dr. Luc Burgun, CEO and president, Emulation and Verification Engineering (EVE)
- Interra Systems
- “Interra is a leading supplier of language front-ends and comprehensive test suites for market-leading EDA standards such as Verilog and VHDL. Interra’s products enable rapid development, adoption and deployment of high quality EDA tools. SystemVerilog is a major advancement for design and verification engineers and Interra plans to offer SystemVerilog solutions starting November 2003. We are working with Synopsys through its SystemVerilog Catalyst program to help establish new levels of consistency and interoperability for all tools using SystemVerilog”
Sunil Jain, CEO, Interra Systems
- Jasper Design Automation
- “As design complexity continues to increase, functional verification has become the dominant problem in the design of a new chip. With the majority of the design cycle spent in verification - and 80% of that time being spent in verification implementation and debug - formal verification is now a must-have tool for verifying complex designs and exhaustively proving design intent. SystemVerilog combines best-in-class modeling with modern verification capabilities, and Jasper Design Automation enthusiastically endorses its adoption while we lay our plans for its support in 2004.”
Kathryn Kranen, CEO, Jasper Design Automation.
- Kurt Baty
- “As an independent consultant designing ASICs and IP blocks for my clients, I am excited at the opportunity to work with tools that support the new design and verification features of SystemVerilog along with the proven extensions provided by Verilog 2001.”
Kurt Baty, WSFDB Consulting.
- Novas
- “Novas has extended its unified debug automation platform to support SystemVerilog design, verification, and assertion capabilities, allowing for the fast detection and repair of complex design problems. We're excited to be partnering with Synopsys and other leading EDA companies to deliver interoperable tools supporting the SystemVerilog standard, to accelerate our customers' schedules.”
Scott Sandler, president & CEO, Novas Software.
- nSys
- “nSys provides efficient, reusable verification IP for designers of complex
SoCs. We've had a lot of success supporting OpenVera Assertion-based
verification solutions. SystemVerilog embeds powerful assertion concepts as
natural extensions to the Verilog language used by our customers already.
We're pleased, therefore, to add our efforts to the growing SystemVerilog
community by including SystemVerilog support for our IP products, such as
PCI Express and other emerging standards that we are working on.”
Atul Bhatia, director, nSys.
- Provis
- “By providing a single simulation language for design, verification and test, SystemVerilog improves tool interoperability and solidifies the target environment for achieving quality design and quality production. Provis is pleased to join the SystemVerilog Catalyst program, and we plan to add SystemVerilog support to Z01X!, our high-speed, high-capacity fault simulator.”
Rich Davenport, president and CEO,
Provis
- Real Intent
- “The SystemVerilog 3.1 language offers design and verification engineers a far more complete foundation for chip and system development than previous solutions. Real Intent has been an strong contributor to the SystemVerilog development effort and plans to deliver formal assertion verification using SystemVerilog in 2004.”
Prakash Narain, president and CEO, Real Intent.
- Sequence Design
- “Providing support for SystemVerilog in our leading RTL and gate-level power analysis product suite, PowerTheater, will bring great benefits, including higher design productivity, to our customers who take advantage of this new and exciting language.”
Vic Kulkarni, president and CEO, Sequence Design.
- SiConcepts
- “SystemVerilog combines the best of hardware design and verification languages; it enables users to rapidly verify complex designs. SiConcepts is excited to join the SystemVerilog Catalyst program to ensure rapid customer deployment of SystemVerilog. This program not only accelerates vendor support, it also hastens wide spread adoption of this important new language. In 2004, SiConcepts plans to provide SystemVerilog design and verification methodology training in partnership with Synopsys.”
http://www.si-concepts.com.
- Summit Design
- “SystemVerilog is an important milestone in the HDL evolution that will allow our Visual Elite users to more simply design and verify complex SoCs. SystemVerilog with its DirectC Procedural Interface (DPI) and transaction level constructs offer a natural synergy with SystemC. Our goal is to provide an integrated design and verification platform that spans from the system-level down to hardware and software implementation and SystemVerilog fits well with this methodology.”
Rami Rachamim, director of marketing, Summit Design.
- Sunburst Design
- “I have personally been involved in the development of every IEEE Verilog language and Verilog RTL synthesis standard. I am excited to be involved with SystemVerilog because of the tremendous benefits it provides to designers. I believe SystemVerilog will deliver the next wave of productivity gains for SoC design companies. I am currently delivering SystemVerilog training and tutorials across the U.S. and I am seeing a lot of interest in adopting the language.”
Cliff Cummings, president, Sunburst Design, Inc.
- Sutherland HDL
- “SystemVerilog marks a new era in high-level design and verification as a true Hardware Description and Verification Language. The SystemVerilog standard's rich modeling extensions to the Verilog HDL enable modeling much larger designs at a more abstract and yet fully synthesizable level of design. Powerful object-oriented and timing synchronized testbench extensions enable verifying these large designs, with all the advantages of writing the test programs in the same language in which the design is modeled. Sutherland HDL is excited to use these SystemVerilog extensions in the consulting and training services we offer. We are thrilled to see how quickly the EDA industry has been adding these important SystemVerilog extensions to their Verilog software tools.”
Stu Sutherland, president, Sutherland HDL.
- SynaptiCAD
- “SystemVerilog's dynamic memory allocation and assertions make it possible to build complex bus-functional models and behavioral golden reference models that are all but impossible to create using only Verilog. SynaptiCAD plans to enhance TestBencher Pro to support generation of SystemVerilog verification environments and test benches from language independent timing diagrams.”
Dan Notestein, president, SynaptiCAD.
- Tenison
- “Our products support industry standards to enable our customers to gain the best productivity and ease of use. Since we already implement part of the Verilog 2000 standard in our VTOC product, we plan to develop support for the SystemVerilog standard extensions also, to better serve our customers’ needs.”
Jeremy Bennett, CEO, Tenison Technology EDA Ltd.
- Tharas Systems
- “Tharas Systems and Synopsys have successfully created an interoperable flow between our Hammer Hardware Accelerator and Synopsys’ VCS simulator and VERA testbench automation products. By extending our efforts to support SystemVerilog we expect to further increase runtime performance and deliver tighter integration to create a more effective verification solution for our customers.”
Rahm Shastry, president and CEO, Tharas Systems.
- TNI-Valiosys
- “Our formal property checker, imPROVE, verifies the behavior of HDL designs without the need for vectors or a test bench, thus enabling engineers to focus on the behavior of their design. SystemVerilog combines and extends the design and testbench elements of today's HDLs with the power of modern assertion-based verification techniques. We are adding SystemVerilog design and assertion support to our tools to ensure our customers gain the most benefit offered by this exciting new standard language.”
Marc Frouin, President and CEO, TNI-Valiosys.
- TransEDA
- “TransEDA’s combination of verification software and IP enable us to offer ready-to-use verification solutions that our customers can deploy quickly as part of a proven design verification methodology. We intend to add support for SystemVerilog as it provides a tremendous opportunity to bridge design and verification, offering engineers a much-needed increase in design productivity and more thorough verification techniques within a single language.”
John Colley, chief technology officer, TransEDA.
- VeriEZ
- “We believe in the value provided by SystemVerilog and are strongly committed to working on tools and technology that can simplify user-migration to SystemVerilog.”
Sashi Obilisetty, president and CEO, VeriEZ.
- Verific
- “As the leading provider of Verilog and VHDL front-ends to EDA companies and CAD groups, moving into the SystemVerilog space comes natural to us. The fact that many of our customers are inquiring about availability already tells us this is definitely the way to go.”
Rob Dekker, president and founder, Verific Design Automation.
- Veritable
- “Veritable views SystemVerilog as a powerful standard that unifies simulation-based verification and formal property checking - taking design and verification to the next level of complexity. Veritable's Verity-Check predictive analysis and formal property checking products will enable customers using SystemVerilog to analyze and formally verify design properties using the same assertions employed during simulation. We are pleased to participate in the Synopsys SystemVerilog Catalyst Program and plan to incorporate support for SystemVerilog into our Design Verity products in Q1 2004.”
Prab Varma, president, Veritable.
- Veritools
- “The new Undertow and Undertow Suite 2003 software provide the Verilog community with fast and comprehensive source code debugging and waveform viewing for RTL and gate-level schematics and state diagrams. Adding into this suite of tools, SystemVerilog's assertions and testbench capabilities will enable more complete and faster design verification. Veritools is pleased to be a member of Synopsys' SystemVerilog Catalyst Program to ensure industry adoption of this important advancement in the Verilog language.”
Robert Schopmeyer, president of Veritools Inc.
- Willamette HDL
- “WHDL is already teaching our training course ‘SystemVerilog for Verilog users’ that shows how to make best use of the exciting new features of SystemVerilog for design and verification. Our clients are very excited by the benefits of the new advanced verification features like assertions and interfaces as well as the reduced ambiguity in RTL descriptions.”
Mike Baird, president, Willamette HDL, Inc.
- XtremeEDA
- "As designs continue to get more complex, SystemVerilog, combined with the right methodology delivers true benefits: faster time-to-market, lower project costs, an open standard, superb features. It's what engineering companies have been waiting for. XtremeEDA embraces SystemVerilog in its verification training and advanced methodology services."
Claude Cloutier, president, XtremeEDA.
|
