ARM, the industry's leading provider of 16/32-bit embedded RISC microprocessor solutions, and Synopsys, the technology leader for complex IC design, have teamed together for several years with R&D partnerships to address designers' leading-edge challenges for system-on-chip (SoC) design.

Low Power Design

• In partnership, ARM and Synopsys have built on their extensive low power collaborative research and silicon technology demonstrators to create the Low Power Methodology Manual (LPMM) for SoC Design, published by Springer. The LPMM enables designers to adopt aggressive power management techniques.


• Focused on leakage management, the Synopsys-ARM Low power Technology (SALT) technology demonstrator SoC showed more than 96% leakage power savings.
• Concurrent with the launch of the LPMM, ARM and Synopsys announced an enhanced implementation Reference Methodology (iRM) incorporating the LPMM techniques for aggressive power management of the ARM1176JZF-S processor subsystem.
• ARM and Synopsys formed an exclusive collaboration to deliver a low-power implementation solution for ARM's Intelligent Energy Manager™ (IEM) technology through the proven multi-voltage, multi-frequency Galaxy™ design flow.


• ARM recommends the jointly developed iRM for implementing ARM IEM-enabled cores, enabling easy adoption of this innovative system-level energy saving solution.
• The collaboration proved the IEM technology in SoCs manufactured at multiple foundries, demonstrating up to 65% energy savings.

Reference Methodologies

• ARM delivers the ARM-Synopsys Galaxy Implementation Reference Methodology (iRM) for RTL-to-GDSII hardening of all soft ARM microprocessor cores. Jointly developed by Synopsys and ARM, the iRM takes advantage of the latest tools including IC Compiler and DC Topographical technology.
• The iRM for ARM's Cortex-A8, highest performance CPU, delivers 5-10X productivity increase with excellent power, performance and area.
• The Synopsys SVP Café directory provides a comprehensive list of ARM processor cores and their support for Synopsys complete design flow.

Libraries And Verification

• ARM's Artisan® Metro™, Advantage™ and Advantage-HS power-aware, multi-voltage libraries, as well as the Power Management Kit (PMK) for these libraries, were developed in close collaboration between the companies.
• Synopsys DesignWare® Library includes synthesizable and verification components for AMBA™ 2 AHB/APB and AMBA 3 AXI interconnect. The coreAssembler tool is also included in DesignWare Library, automating the process of configuring, assembling, implementing and verifying an AMBA bus-based subsystems.
• ARM and Synopsys have jointly developed a reference verification methodology based on SystemVerilog and co-authoring the SystemVerilog Verification Methodology Manual - a "how-to" book on advanced verification techniques using SystemVerilog.
                  
• A joint system-level design solution enables software development and verification of ARM processor-based SoCs.
• The Synopsys SVP Café directory provides a comprehensive list ARM Artisan physical IP (libraries) along with their support for Synopsys’ complete design flow.

Professional Services

• Synopsys Professional Services co-developed the ARM-Synopsys Reference Methodology and IEM Reference Methodology, and has extensive experience hardening and integrating ARM cores in SoCs.