In line with its broad focus on low power, Synopsys recently acquired ArchPro Design Automation, a leading provider of low voltage tools in the verification domain. ArchPro's technologies enable engineers to address power management challenges in multi-voltage designs from chip architecture to RTL and gate-level design. These technologies allow verification of modern power management techniques such as power gating, substrate biasing, dynamic voltage and frequency scaling, and extend Synopsys' leadership in low power design and verification. ArchPro is being used today on a variety of wireless and digital consumer applications and has achieved over 25+ tape-outs.

In addition, Synopsys recently introduced the Low Power Methodology Manual, a comprehensive and practical guide to managing power in system-on-chip designs, critical to designers using 90-nanometer and below technology. Combining extensive commercial experience, deep scientific understanding, silicon technology case studies, and a pragmatic approach, the authors describe design techniques which address both dynamic and static (leakage) power, including methods for power gating and dynamic voltage and frequency scaling. For each topic, the authors describe the design challenge, provide a technology foundation, and then make specific recommendations as well as a caution against design pitfalls. This book is a must-read for anyone designing, or getting ready to design, SOC's for low power applications. Visit us at VLSI Fair in January 2008 to hear even more.

This manual is endorsed by many super users including Wipro. Sujeeth Joseph, Chief Architect - Semiconductor & System Solutions Unit, Wipro Technologies, said, "Excellent compendium of low power techniques and guidelines with balanced content spanning theory and practical implementation. The LPMM is a very welcome addition to the field of low power SoC implementation that has for many years operated in a largely ad-hoc fashion."

In this newsletter, read about Tessolve’s recent success in reducing cost of test. To address this need, Tessolve, a start up in the Test design services arena, has come to the forefront. SNPS, India enabled them with flexible license models, training and provide the best in class tools. This furthers Synopsys’ commitment to work closely with start ups and be a major player contributor to the Semiconductor ecosystem and growth of the industry in India.

Earlier this season, we concluded three very successful low-power seminars in Noida, Hyderabad, and Bangalore on the 6th, 8th, and 10th of August respectively. These seminars are a forum for members of the electronic design community to get the latest information on design automation solutions and methodologies. Intended for IC design and verification engineers and managers, these technical seminars enable you to deliver the best products to your customers with predictable success. Topics like Synopsys’ Galaxy Design Platform; enhancements in RTL synthesis, DFT, physical implementation, sign-off, low-power design, and design-for-yield techniques; and silicon-proven case studies were covered in great detail with compelling customer keynotes delivered by ST Microelectronics in Noida and Redpine Systems in Hyderabad. Stay tuned for more seminars planned in 2008.

Finally, a few of Synopsys’ notable achievements for you:

Business

• Double digit growth in revenue and earnings per share
• Revenue grew 10% year-over-year growth to $304M
• On track to achieve operating margin of 20% in FY07

Market Momentum

• Majority of 65-nm & 45-nm designs are being taped-out using Synopsys physical tools
• IC Compiler enjoying business and technology success NEC achieves 2X performance improvement and meets power budget; Toshiba is standardizing on IC Compiler for its highly automated, multi-voltage low-power flow
• PrimeYield qualified for TSMC’s 8.0 reference flow
• Expanded our IP portfolio by acquiring the assets of Mosaid, a leader in DDR cores

Happy Reading!

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