| Technology Update|
Doubling Productivity of Synthesis and P&R with Design Compiler 2010
Design Compiler® 2010 provides a better starting point for physical implementation, which is helping design teams to double productivity throughout the entire design flow. Gal Hasson, Synopsys, outlines some of the key features in Synopsys’ latest release of its synthesis product.
The Design Compiler story is one of continuous development and innovation. In delivering improvements, our aim has always been to keep pace with the demands of both the latest process technologies and the design teams that use them.
Alongside our on-going efforts to improve quality of results and runtime performance, we have also introduced many new technologies over the years to help designers manage emerging issues in areas such as design for test, ATPG and power-aware design. We carefully track the effects that our enhancements have on a range of important parameters (Figure 1).
Figure 1: Improvements in Design Compiler from Continuous Innovation
Looking Back to the Beginning of Look-ahead
The more significant innovation we have made over the past five years is the introduction of look-ahead optimization using topographical technology. This was important because it eliminated the use of wireload models, instead using actual physical information from the place-and-route process in order to improve correlation between front- and back-end design processes. By sharing technology with IC Compiler, we achieved 10% timing correlation between synthesis and layout, which was instrumental in limiting the number of iterations between synthesis and place and route.
In our subsequent 2008 release we extended topographical technology to enable designers to predict, visualize and then fix routing congestion.
We were responding to a fundamental change in chip timing at the time we introduced look-ahead optimization: interconnect delay had overtaken gate delay as the dominant timing effect, and to counter this we needed a better starting point for place and route.
In 2010, interconnect delay continues to dominate. The combination of higher wire lengths and reduced spacing increases coupling capacitance. This accentuates the impact that wire length and cell placement has on critical paths. There is also a danger of severe routing congestion, which will dictate the need for further layout changes. The net effect is that, once again, designers are at risk from an increase in the number of iterations between synthesis and place and route.
A Better Starting Point
Achieving the best possible starting point for physical implementation has become imperative in tackling complex designs that have demanding project schedules. Avoiding the ‘ping pong’ effect between synthesis and physical design will reduce the number of iterations needed in order to achieve design closure, and lead to an overall more productive design environment. As in 2005, this requires even tighter links between synthesis and physical design.
To provide a better starting point for physical design, we have made two key improvements to the 2010 release of Design Compiler: push-button floorplan exploration and physical guidance to IC Compiler.
Push-button Floorplan Exploration
By making IC Compiler floorplanning accessible from within Design Compiler, RTL designers can easily explore a range of floorplan options and fix any floorplan issues within synthesis. For example, designers can identify issues like congestion within Design Compiler and easily edit the floorplan to eliminate the congestion before place and route.
This approach leads to faster convergence on an optimal floorplan without having to hand off the design between synthesis and floorplanning several times, so it addresses a common drawback of the traditional way that designers link between front- and back-end design teams.
The push-button approach supports both floorplan creation and modification. Once finished, the RTL designer can hand off the optimal floorplan with the synthesized design to the back-end design team for place and route.
Physical Guidance to IC Compiler
We have extended Topographical technology in Design Compiler 2010 to create physical guidance for IC Compiler bringing synthesis timing and area results within 5% of layout while speeding up IC Compiler placement step by 1.5X.
Topographical technology performs additional physical optimizations – some new to synthesis, such as timing-driven placement optimizations, which result in a better starting point for place and route. Seeding IC Compiler placement through physical guidance streamlines the implementation flow and accelerates placement runtimes.
We have also introduced other important enhancements, such as improving the modeling accuracy of coupling capacitance and interconnect delays by taking cell density into account.
Figure 2: Correlation between Design Compiler and IC Compiler within 5%
In line with our strategy to provide support for multicore compute environments, we have introduced a new multicore infrastructure with an optimized scheme that incorporates both distributed and multithreaded techniques for Design Compiler. This delivers an infrastructure for scalability with no deviation in quality of results. The changes boost runtime by around 2X using platforms with four cores.
The enhancements we have made to Design Compiler 2010 add up to a 2X increase in productivity across the entire implementation flow – both in synthesis and physical design. The key to this is using techniques to improve the starting point for physical implementation with physical guidance and push-button floorplan exploration. Simultaneously, we have improved the correlation between Design Compiler and IC Compiler to 5%. For those design teams using multicore compute platforms, a further 2X speed-up in synthesis runtime is possible by deploying the tool on a four-core machine.
Ultimately, bringing synthesis, floorplanning and place and route closer together ensures faster convergence on an optimal floorplan and predictable design closure. This minimizes the iterations for design teams, while helping them to meet their design goals in shorter timeframes.
Design Compiler 2010 floorplan exploration and physical guidance to IC Compiler capabilities are available to customers with the 2010.03 release of Design Compiler Graphical. The multicore runtime speedup is included in DC Ultra 2010.03, both of which are now available within the Synopsys GalaxyTM Implementation Platform. Customers are reporting shorter schedules, reduced iterations and faster placement as a result of adopting Design Compiler 2010.
"For the last few years, we have used Design Compiler's topographical technology to find and fix design issues during synthesis to give us predictable implementation. We see Design Compiler 2010 synthesis results closely correlating to physical results, while accelerating placement in IC Compiler by 1.5X. This tight correlation between synthesis and layout, along with faster runtimes, is exactly what we need for reducing iterations and significantly shortening design schedules in 65 nm and smaller process technologies."
Shih-Arn Hwang, deputy director R&D Center at Realtek
"Cutting design time and improving design performance are essential to keep our competitiveness in the marketplace. With the new physical guidance extension to topographical technology we are seeing 5% correlation between Design Compiler and IC Compiler, up to 2X faster placement in IC Compiler and better design timing. We are adopting the new technology innovations in Design Compiler to minimize iterations while meeting our design goals in shorter timeframes."
Hitoshi Sugihara, department manager, DFM & Digital EDA Technology Development at Renesas Technology Corp.
Gal Hasson is senior director of marketing, RTL synthesis, power and test automation at Synopsys.
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