| Technology Update|
Solving SoC Verification Challenges
Successful, on-time delivery of the latest multimedia SoCs places tremendous pressure on engineers to complete verification quickly and efficiently. Michael Sanie and Badri Gopalan, both Synopsys, summarize the key verification technologies that can help to ease the pressure.
Today’s high-end multimedia platforms illustrate just how complex SoC designs have become. They combine multiple communications protocols, like 3G broadband, Wi-Fi and Bluetooth, with demanding 3D graphics and HD video. For some applications, integration with navigation and mapping features adds another set of tasks for the processor to handle. Table 1 shows how design complexity has exploded over the past 10 years.
Table 1: Leading-edge SoC complexity 2000 and 2010
Hitachi’s SH-Navi3 processor is a case in point. This processor combines features for automobile safety, navigation and entertainment. Combining all of these functions in a single chip requires integration of high-performance processor and graphic cores, embedded image recognition, vehicle control technology, GPS and multimedia functions. Hitachi’s architecture includes two processor cores running at 533 MHz, a 2D/3D graphics accelerator, 53.3 GOPS image recognition engine, PCI Express, and DDR3. The device will operate at temperatures of between -40°C and 85°C. Verifying all of these functions in isolation is a difficult enough task. Verifying the system as a whole puts new demands on verification teams, tools and methodologies.
The SoC Approach
The use and re-use of IP now dominates SoC design. Design teams can procure IP from third-party suppliers and from within their own organizations in order to build their SoCs more productively and cost-effectively. Design teams typically turn to available IP for their processor cores and, increasingly to support the myriad of advanced interface protocols, such as USB and SATA, which are now a key part of many of today’s SoC designs.
Moving from a “monolithic” approach to IP-based SoCs has also changed the way that engineers approach design verification. IP-based design has changed the objective of the design and verification process to quickly move from block-level design and verification to system integration and system-level verification.
As well as meeting the functional verification needs, verification engineers often have to consider additional aspects in verifying certain application-specific chips. For example, mobile/handheld SoCs have stringent low-power requirements that affect the verification process. Similarly, wireless SoCs incorporate analog/RF circuitry that requires special treatment when it comes to verification.
The importance of embedded software in the chip world has grown enormously over recent years. Design teams see software as the key to differentiate their products, and the availability of the right software apps has greater consumer appeal than hardware features like performance or memory. The other important benefit of software is that product manufacturers can use it to add new features or capabilities, create new derivative products on the same hardware platforms, or even work around hardware bugs. It’s not surprising that design teams are increasingly looking for verification solutions that allow them to verify software-hardware integration.
Business Drivers for Verification
New demands on SoC design are re-shaping the business drivers for verification tools and technologies.
Fast Verification Turnaround Time
The biggest single factor in determining the profitability of any chip project is timing. Project schedules are vital for any SoC engineering team that wants to get their products to market on time. For this reason, SoC engineering teams require a verification solution that provides the fastest verification turn-around time. This requires an optimal combination of compile-time, run-time, debug and coverage convergence, and the ability to take advantage of the latest computer architectures, including multicore processors and compute farms. Efficient use of memory capacity remains an important tool attribute for the verification of large SoCs.
Verification IP (VIP)
Having access to high-quality VIP complements the SoC design approach. It simplifies testbench development, provides better coverage and delivers significant improvements in simulation runtime performance. When verification teams source VIP for standard blocks, they can use it to speed up development by generating bus traffic and checking for protocol violations.
One of the most challenging issues for engineering teams is to figure out when they have done enough verification. Having tools that report on metrics like functional coverage, code coverage, and assertion coverage assists engineers in making rational decisions about verification completeness.
Power-stringent SoCs need verification solutions that include advanced capabilities to verify multiple voltage domains and their interactions. Power-aware verification must also be able to handle schemes for scaling frequency and voltage, as well as power management strategies.
To address the need for on-time verification delivery, system integration and verification at both block- and system-level, engineering teams need to plan their verification strategies and have structured verification methodologies.
For SoCs with analog and RF, verification requirements include analog/mixed-signal modeling and additional capabilities such as co-simulation, digital real-number modeling and related methodologies.
FPGA-based prototyping and debug provide many verification teams with higher productivity and lower infrastructure cost for hardware/software verification and “at speed” system validation, and help them to find “corner case” hardware bugs. Virtual prototyping systems enable SoC design and verification teams to start software development and integration before the silicon becomes available.
VCS Functional Verification Solution
The continued growth in design complexity has made verification the most significant challenge in the SoC design process today. Synopsys’ ongoing investment in advanced verification technologies is helping to address the needs of engineering teams working on leading-edge chip projects across several market sectors.
According to Synopsys’ market analysis, VCS is the verification solution used on more than 90% of designs targeting processes at 32 nm and below, and on 60% of 45 nm designs. These leading-edge SoC projects span several industry segments and use models, including processors, graphics and networking.
Synopsys’ market leading position in advanced verification solutions comes as a result of introducing innovative technologies. Figure 1 shows the continued technology investments in VCS that have enabled Synopsys to keep pace with the explosion in design complexity.
Figure 1: Continued technology investments in VCS
VCS offers the industry’s highest capacity and best performance, a robust constraint solver, low power verification, and unified coverage capabilities, including verification planning, functional, assertion, formal and code coverage. VCS also provides advanced technology such as design-level parallelism and application-level parallelism with VCS multicore, Echo testbench coverage convergence, and transaction level debug to further boost verification performance and productivity.
To learn more about how industry leaders verify with VCS, please visit our webpage for the latest white papers, articles and webinars.
About the authors
Michael is director of verification marketing at Synopsys.
Badri is a principal engineer in the verification group at Synopsys.
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