Innovative Ideas for Predictable Success
      Issue 2, 2010

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Verifying Implantable Medical Devices
It takes a lot of transistor-level simulation to design devices for implantable medical products. In their search for ‘out-of-the-box’ speed and accuracy, Garret Marshall, Scott Stanslaski, and Jalpa Shah from Medtronic measured speed, accuracy, ease of use and time to results for two full-chip analog simulators. This article is based on their award-winning paper first presented at Boston SNUG.

Generally, people don’t like to go under the surgeon’s knife too often, so the implantable devices we design to manage things like cardiac rhythm must last for at least seven years. Consequently, current drain and battery life are a big deal for our design teams. We need accurate analysis of current drain to verify chips for implantable products, so it’s not surprising that full-chip analog simulation is a mainstay of our design process.

Unfortunately, verifying analog circuits is one of the main bottlenecks in IC design. What makes it worse is that our circuits use slow clock speeds, which can mean that we have to run simulations for hundreds of milliseconds, if not seconds, to properly verify them.

Our Ideal Simulator
We use both behavioral modeling and Synopsys’ Fast-MOS simulator, NanoSim, to help increase simulation throughput. However, both approaches have drawbacks. When using behavioral models, we need a methodology to identify:
  • what to put in the model
  • how to verify it
  • when to use it, and
  • the circumstances in which we need to update it.

Improperly encoded models can cause inaccurate results and simulation performance issues, so we have to take care when writing them.

To achieve optimal results with NanoSim, you have to use it often enough to become expert at modifying the settings for netlist optimization, device model optimization, and simulator accuracy. Even with a good working knowledge of NanoSim, this typically takes a week or so for each circuit.

Ideally, we want a simulator to be SPICE-accurate and deliver high performance without having to spend a lot of time setting it up. This requirement has led us to evaluate and compare a number of FastSPICE simulators. We looked at ease of use, simulation speed, accuracy, and power reporting capabilities.

Test Circuit 1: Crystal Oscillator
We chose a crystal oscillator as our first test circuit. It is a traditional Pierce oscillator design that provides a 100 KHz clock using a 0.8 μm HV BiCMOS technology (Figure 1). The oscillator includes an amplifier and a comparator that, together with the crystal, generate oscillations. The circuit includes a bias block to provide bias current for the oscillator, POR to generate an analog reset and a clock monitor to provide an OSC_OK signal after the oscillator stabilizes. The crystals have a very high quality factor (Q), which means that it takes longer for the oscillator to start up and reach a steady state. In order to simulate this block we reduced the Q to 100 instead of 40K. The block has a clock monitor that waits 4096 cycles before setting OSC_OK high, signaling that it is ready to use.


Figure 1. Oscillator Test Circuit

It can be tricky to get oscillators to start oscillating, so we expected to have to modify the simulation setup. Initially the simulation ran slowly, which we addressed by turning on double-precision accuracy. You might expect the use of double-precision arithmetic to be even slower. However, because it is more accurate the tool can reduce the level of artificial noise it has to inject. Using a lot of artificial noise greatly increases the simulation times. We could verify this by looking at the waveform and checking the results, which showed that without double precision, the simulation was actually incorrect.


Figure 2. Oscillator Simulation Results (NanoSim)

The top waveform in Figure 2 shows OSC_OK going high when the oscillator stabilizes. The bottom waveform shows the oscillator output from NanoSim (green) and our golden simulator (gold). The NanoSim waveform is much noisier than the golden simulator, which has an impact on accuracy. This simulation ran for 372 minutes on a 2.9 GHz Linux machine.


Figure 3. Oscillator Simulation Results (XA)

The Figure 3 results show that the accuracy of XA (green) is almost equivalent to our golden simulator. This simulation ran for 77 minutes on a 3.6 GHz Linux machine.

Test Circuit 2: Brain Radio
The brain radio is a design from our Neuro Modulation Business Unit. It uses three brain-sensing channels and includes blocks such as chopper-stabilized amplifiers, bias generators and power supplies (Figure 4).


Figure 4. Brain Radio Test Circuit

Two of the channels are power spectrum measurements and one is a wide-band time- domain channel. We tuned the two power spectrum channels for 30 Hz (Band_Power<1>) and 60 Hz bands (Band_Power<3>). A swept sine wave of 10 μV is injected into the channels with increasing frequency to determine the sensing channel performance.

In this simulation there is a layout parameter extraction (LPE) issue present in Band_Power<3> that causes it to have issues settling at the 60 Hz band. Band_Power<1> settles quickly because the LPE issue does not impact the design at maximum gain and 13 – 30 Hz band measurements. This issue is present only at the maximum gain setting and not at the bands of interest for this project, which are 13-30 Hz and 100 Hz. Using XA, we discovered that the LPE issue was due to a 0.054 fF coupling capacitor from a clock line to the input of the chopper amplifier.

For this simulation the design testbench is a schematic and the circuit netlist uses the Spectre format. The testbench uses a Verilog-A model to generate the injected sine wave of 10 μV with increasing frequency. In the simulation, there are five RC oscillators running for each of the four sensing channels. We designed the clocks to provide a nominal 50% duty cycle to suppress sensitivity to even harmonics. To minimize the impact on the power budget, we allocated the clock 200 nA per channel. We can adjust the clock frequency with programmable capacitive trims from DC to 500 Hz in 4 Hz steps. To minimize drift, the microprocessor routinely calibrates the clocks by comparing periods with the crystal oscillator embedded within the existing neurostimulator. Relative clock matching is critical for robust operation of the circuit, and our results will demonstrate that we can achieve acceptable performance for our application.

Initially we attempted to simulate this design using NanoSim, but even after investing a considerable amount of time in trying to fine-tune the accuracy and speed settings, we didn’t get the results we wanted. Instead we focused on using XA.


Figure 5. Brain Radio Simulation Results (XA)

The simulation took 226 minutes on a 3.3 GHz Linux machine. Band_Power outputs in Figure 5 are the raw outputs of the power spectrum signals.
  • Band_Power<0> is the output of the wide-band sensing channel 1
  • Band_Power<1> is the channel 2 trimmed to 30 Hz. It settles quickly even with the LPE issue
  • Band_Power<3> is the channel 4 trimmed to 60 Hz and being impacted by the 0.05 fF capacitor. This signal should mimic Band_Power<1>

Simulation Flow
Our designs are typically mixed-signal. We often capture the top level structure as a Verilog netlist (Figure 6).


Figure 6. Typical Netlist Partitioning

The way we partition our designs leaves us two ways to verify an analog block. We can do a mixed-mode simulation using the entire IC, or if we need to verify an individual block, we can use a schematic testbench.

Some analog block-level interactions cannot be verified by individual block-level verification so another schematic testbench is used to stitch multiple analog blocks together with their pad connections. The major drawback of this methodology is that the designer isn’t actually verifying the tapeout netlist, so we need to take extra care to ensure the connections are correct. This approach also makes it harder to stitch layout parasitics into the post-layout simulation.

We have used NanoSim for all scenarios to verify functionality and timing, as well as current drain. If we need current drain measurements for the entire IC, then we’ll use a digital testbench environment and feed the entire IC into NanoSim. When doing current drain measurements, NanoSim reads the Spectre netlists for the analog blocks, a Verilog gate-level netlist, and Spectre netlists for all the instantiated digital cells, including pads. For our 0.8 μm HV BiCMOS technologies, the post-layout flow requires a lumped or cross-coupled capacitance extraction. We then use a Perl script to create the appropriate Spectre format for back-annotation from the extracted netlist. For our 0.25 μm technologies, the post-layout flow is to perform distributed RC extraction using the SPEF format. This flow is much more desirable because the resulting layout extraction netlist doesn’t need to be post-processed using a Perl script.

Simulator Comparison
NanoSim gave us a 4.3x improvement in simulation time compared to our golden simulator and XA gave us a 31X improvement and much better accuracy (Table 1). XA offers much better accuracy than NanoSim. We found simulation setup times to be high for both NanoSim and XA because both simulators required several iterations to dial in the accuracy and speed.


Table 1. Comparing simulation time and accuracy for NanoSim and XA
for the oscillator test circuit

For the brain radio circuit, NanoSim worked with no layout parasitics, although simulation times were very long (more than eight hours). Despite changing various settings, NanoSim didn’t cope well with layout parasitics for this design. The simulation time exploded and gave very inaccurate results.

To our amazement, we were able to run XA with its ‘out-of-the-box’ settings and it gave us fast results, and everything was correct except for Band_Power<3>. Because this was a new simulator, our first response was that it must be an XA tool issue. The Synopsys application engineer worked hard to prove that the erroneous results were not due to a model or tool issue.

On closer examination, our Synopsys applications engineer found a .054 fF layout parasitic coupling capacitor that was coupling a clock line to the input of the chopper amplifier, which caused the functional issue.

When compared to our golden simulator, XA out-of-the-box (set_sim_level 3) gave us a 20.5X improvement in speed, but didn’t produce the accuracy we wanted. Using set_sim_level 6 we achieved the accuracy that we desired with a 9.3X improvement in speed. Table 2 lists simulation times, accuracy, and simulation setup ease of use for NanoSim and XA for the brain radio circuit.


Table 2. Comparing simulation time and accuracy for NanoSim and XA
for the brain radio test circuit

Conclusions
XA is much easier to use, more accurate, and at least five times faster than NanoSim. Comparing usability, NanoSim has over 250 configuration commands compared to approximately 40 for XA. Its simpler approach gets new and existing users of XA up and running in a third of the time compared to NanoSim. In our testing we also found XA to be 5X more accurate than NanoSim.

In the case of the oscillator, it was not intuitive that we would have to raise the ‘set_sim_level’ to level 6 to achieve faster run times and good accuracy. For the brain radio circuit it was very easy to setup XA, whereas with NanoSim we couldn’t get the simulation up and running with layout parasitics.

Without XA, we would not have found the 0.054 fF coupling issue. The only way to find this kind of issue is to simulate the entire design at the transistor-level with full-chip layout parasitics.

Our ideal fast-SPICE simulator is fast and accurate out-of-the-box and doesn’t require any fine tuning of commands for accuracy or speed. Although XA still requires some fine tuning to dial-in accuracy and speed, it is definitely a step in the right direction.

About Medtronic
Through its key businesses, Medtronic partners with medical professionals to develop life-changing technologies that improve the way chronic diseases are treated.

Biographies
Jalpa Shah was born in Gujarat, India. She received BE (EE) degree from Gujarat University, India in 2005, and MS (EE) from Georgia Institute of Technology, GA in 2007. During her masters, she worked on designing CMOS interface ICs for MEMS Gyroscopes. She joined Medtronic in 2008 as an Analog IC design engineer. Currently, her work involves analog circuit design for neurostimulators.

Scott Stanslaski received his BSEE degree from the University of Minnesota in 1993 and MSEE degree from the University of Minnesota in 2000. Scott has worked for Medtronic for 14 years as an analog circuit designer on medical implantable products. The first 13 years were spent working on Cardiac Rhythm devices including pacemakers and defibrillators. The last year has been spent working on new Neuromodulation devices.

Garrett Marshall received his BSEE degree from the University of Illinois @ Urbana-Champaign in 1998 and his MSE degree from Arizona State University in 2001. Garrett has worked with Medtronic for 12 years. The first 4 years were spent doing mixed-signal IC design work for glucometers. The last 8 years have been spent doing electrical design automation.


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“XA is much easier to use, more accurate, and at least five times faster than NanoSim.”