| Technology Update|
Coping with Modern AMS Verification Challenges
Bradley Geden, product marketing manager, Synopsys, describes how Synopsys customers are overcoming the challenges they face in verifying complex AMS design by using CustomSim™ unified circuit simulation to deliver advanced products on time.
The convergence of computing, consumer and mobile applications means that design teams must integrate complex digital and analog functions with increasing amounts of memory on a single chip. With higher levels of integration comes a new set of AMS verification challenges, which are exacerbated by increasing transistor device model complexity with shrinking nanometer processes.
Nanometer Process Complexity
Process engineers have to create increasingly complex transistor-level device models in order for designers to accurately simulate circuits targeted at nanometer process technologies.
The number of instance parameters required to model the physical effects on a device’s performance has increased by more than 6x from one process node to the next. These instance parameters account for layout -specific effects (well-proximity effects – WPE, LOD, stress-related effects), aging effects (NBTI, HCI, electromigration) and so on.
Synopsys has partnered with TSMC to develop a custom compiled C-model (TMI) for TSMC’s 40nm process node and below. Synopsys and TSMC have optimized the TMI model and circuit simulators (HSPICE® and CustomSim) together. This improves simulation performance over traditional sub-circuit based approaches.
Early adopters of new process technologies must have device models and circuit simulation solutions ready when design work begins. To achieve this goal, Synopsys works with foundries to get early access to device models, and with customers to access their design data. This ensures that the circuit simulation solutions are ready to meet customer requirements at the early stages of process adoption.
Larger Designs, Complex Analog Functions
To verify today’s modern-era AMS designs, engineers need a unified circuit simulation solution that can efficiently verify different classes of circuits, including custom digital, analog and memory. To reduce the impact of process variation, designers are using digital control to monitor and fine-tune analog circuit performance after fabrication. Therefore any circuit simulation solution needs to deliver the performance and accuracy required to efficiently simulate emerging design styles. These include digitally controlled analog functions such as RF transceivers, PLLs and sigma delta converters.
Less Power, Smart Power
Process engineers do what they can to reduce leakage power using new materials and processing techniques. Design engineers still need to employ a number of advanced power reduction techniques, such as power gating, multi-VT and dynamic voltage scaling – all of which need a central power management unit to control them.
Consequently, a modern-era AMS system-on-chip (SoC) has many different modes of operation. Designers need to verify these modes individually to ensure that the control unit powers functional blocks up and down with the correct supplies, and in the correct state. Comprehensive verification requires long transient simulations, which can take days and weeks.
When verifying power management circuitry, designers need to check for leakage power by monitoring when individual blocks power down. Designers also need to check power supplies are hooked up correctly and confirm there are no wasted DC paths. These additional tasks are time-consuming and difficult to verify with simulation alone. Designers need a solution that can perform these checks natively during transient simulation.
Circuit Simulation Needs
The current trends influencing AMS verification include process-related challenges, power management verification and lowering the overall product life-cycle costs.
Traditionally, tool vendors have developed circuit simulation technologies that they have optimized to deal with one particular block type, such as custom digital, memory or analog.
What designers need today is a comprehensive circuit simulation solution, from RTL to transistor level, which provides a combination of best-in-class technologies for high-performance full-chip verification. A comprehensive set of native checks for both static and dynamic circuits will help designers to be more productive when checking the design for violations of electrical rules.
The complete circuit simulation solution needs to be supported by an AMS verification methodology built on analog assertions. A predictable verification methodology allows verification engineers to ensure that the complete design specification is covered during regression testing and that errors are flagged immediately through analog assertions and automated checkers validate circuit functionality providing a single click verification process to help guarantee first pass silicon success and hence reducing product life-cycle costs.
The CustomSim Unified Circuit Simulation Solution
CustomSim addresses the AMS verification needs of large nanometer designs by combining the three best-in-class simulation engines of NanoSim®, HSIM and XA Technology in a single, unified circuit simulation solution. CustomSim works with Synopsys’ VCS® simulator through a Direct Kernel Integration, which enables full-chip verification. This comprehensive offering also introduces native circuit checks into the AMS domain and integrates with a unified AMS verification environment. A common set of inputs, outputs, device models and debug features makes the verification environment easier to use.
Figure 1. CustomSim unified circuit simulation solution
CustomSim Native Circuit Checks
The CustomSim native circuit analysis options provide a comprehensive set of static and dynamic checks. These checks, including pre-simulation design analysis, DC static analysis, transient dynamic analysis and post-simulation waveform analysis, are invoked at different stages of the design cycle. The inputs to these stages include the design, extracted post-layout data and the native circuit check command file.
The solution increases productivity by providing a number of pre-defined checks that designers can use immediately. They can also customize the pre-defined checks using an extensive command syntax and programmable interface. Examples of violations that designers can check for include:
- Maximum ratings for safe device operation
- Incorrect substrate connections
- Excessive leakage due to erroneous connection between different supply domains
- Potential leakage path due to floating gates
- Standby current estimation
Figure 2: Finding common errors with native circuit checks
Many customers have successfully adopted the CustomSim solution to meet their verification needs and have published results of their experiences extensively in SNUG user papers. At a recent AMS verification event held at DAC in San Francisco, panelists from Sun Microsystems, Altera, Texas Instruments and ST Microelectronics delivered presentations on the AMS verification challenges they face today and how the CustomSim solution is addressing their needs.
Sun Microsystems provided valuable insight into the growing complexity of process device models, highlighting a 6x increase in instance parameters and a 20x increase in model card complexity. CustomSim addresses the verification needs of Sun Microsystems who use all three engines to verify their advanced nanometer designs. NanoSim is used for early behavioral and Verilog analysis, HSIM large blocks with arrayed structures and XA for circuits that are more analog/mixed-signal in nature (PLL, ADC, etc.).
Altera aggressively adopts new process technologies and highlighted one of the keys to its success as its effective partnership with Synopsys and its foundry partners to deliver circuit simulation solutions when design work begins. Altera is using the CustomSim solution at 40nm and is now qualifying the solution for 28nm.
ST Microelectronics bases its CMOS, NVM and Smart Power technology simulation flows predominantly on Synopsys engines. It uses CustomSim for full-chip pre-layout and post-layout simulations that deliver an impressive gain in terms of speed with high accuracy within 3-5% of their ‘golden’ SPICE simulator. At ST, CustomSim enables three different verification flows, namely transistor-level simulation, design safety checks and co-simulation.
Rising to the Challenge
This article has discussed some of the toughest verification challenges that semiconductor companies face today, including complex device models, digitally controlled analog functions, power management techniques and full-chip verification of designs including analog, custom digital and memory blocks.
AMS design and verification is not getting any easier and as technology progresses to 28nm and beyond, the verification challenges will continue to increase. Synopsys continues to invest heavily in circuit simulation technologies while closely collaborating with customers and foundries. In doing so, it offers a unified circuit simulation solution that helps customers to achieve their verification aims.
Bradley is the product marketing manager for Synopsys circuit simulation products. He received his bachelor degree in electronic engineering from the University of Pretoria in South Africa. He started his career as an analog/mixed-signal IC design engineer at the SAMES wafer fab in Pretoria. Subsequently, he joined CML micro in the UK where he was responsible for leading IC design teams delivering products to the wireless and wireline markets. Over the last eight years he has held product marketing and sales positions at Mentor Graphics and Synopsys.
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