| Technology Update|
Parasitic Extraction for Next-generation Custom IC Design
Designing custom and mixed-signal circuits for the latest process technology demands high-accuracy extraction that is tuned for simulation productivity, explains Shekhar Kapoor, senior product marketing manager for signoff products at Synopsys.
The widespread use of custom circuits in today’s complex system-on-chip (SoC) designs is creating an increased accuracy concern and a severe design and analysis bottleneck. Increasing transistor counts combined with the modeling of more complex parasitic effects is resulting in transistor-level simulation runtimes doubling and quadrupling.
Parasitic extraction technology is a key concern for design teams, not just because it determines how accurate simulations are, but also because the results of parasitic extraction can have a dramatic effect on simulation performance.
Synopsys has recently extended its Galaxy™ solution to incorporate custom design capabilities with the addition of Galaxy Custom Designer. Now, it is expanding its extraction capabilities within the Galaxy platform with StarRC™ Custom.
Figure 1. Synopsys Galaxy Platform for Custom Design
Synopsys took a unique approach with StarRC Custom by focusing on extraction runtime and accuracy, as well as tuning the extraction data to improve transistor-level simulation throughput and overall design productivity.
Business and Technology Drivers
The convergence of consumer applications requiring wireless operation for mobility is leading to an increased mix of digital and analog design and greater use of custom circuits in today’s system-on-chip designs. It is estimated that over 80% of SoCs now use custom or analog mixed-signal IP blocks, which are critical to design performance and functionality. Because analog circuitry is so much more sensitive to noise than digital, designers need to be sure that they can very accurately extract the IP, simulate it and sign it off.
A second trend is the emergence of new parasitic effects. As designers move to smaller geometries, increased process variation causes new issues, particularly for highly sensitive custom circuits. Designers now consider some second-order parasitics to have a first-order effect on device performance. It takes advanced modeling of the new parasitic effects and very precise extraction to achieve the desired silicon behavior.
A third trend is that simulation runtimes continue to get longer. In fact, they increase 2–4x with every new process technology because of growing complexity and escalating parasitics. Designers are looking for faster turn-around times in order to finish their designs on schedule, especially given that verification already accounts for more than 70% of the time they spend developing a chip.
It is essential that the extraction solution for today’s advanced custom designs provides a high degree of accuracy in parasitic modeling, as well as efficient links with simulation and implementation to accelerate turn-around time. Synopsys’ StarRC Custom parasitic extraction addresses these needs: the solution is specially architected for custom design at 65nm and below.
StarRC Custom Key Technologies
Synopsys has developed StarRC Custom to deliver gold-standard extraction accuracy. Designers will use it for interactive design of custom blocks and for cell or IP characterization, where the emphasis is on accuracy over high capacity. For custom IP and standard cell development, designers will realize reasonable extraction and simulation times.
Synopsys took Star-RCXT™ extraction technologies and combined them with the Raphael™ NXT 3D fast field solver to produce a single, unified extraction solution. The result is a high-performance product with user-selectable accuracy levels.
StarRC Custom has optimized links to Synopsys CustomSim™ circuit simulator, which provides a 10x boost in simulation runtime and maintains signoff-level accuracy. Designers benefit from better productivity because of its seamless integration with Galaxy Custom Designer. For example, from within the Custom Designer cockpit, users can set up extractions, run StarRC Custom, and directly analyze the results by viewing the netlist or physical layout circuit.
Gold Standard Extraction
The industry has long recognized Synopsys as having the most advanced process modeling technology in its Star-RCXT product. Its benefits include sub-femto Farad accuracy and high performance, which it achieves using ScanBand extraction capabilities. Foundries have traditionally used Synopsys’ Raphael NXT’s 3D field solver extraction technology to provide reference-standard accuracy for their test structures.
Combining both technologies has enabled Synopsys to develop gold-standard extraction technology that offers designers high performance, and accurate and flexible extraction. This approach allows designers to select accuracy and performance levels to match their exact needs. For example, for sensitive circuits or smaller structures, using the embedded Raphael NXT 3D extraction engine seamlessly within the same environment will provide higher levels of absolute accuracy.
Figure 2. Unified Gold-Standard Extraction Technologies
The golden Star-RCXT technology provides full-chip performance and capacity, allowing designers to extract 10 million or more nets with sub-femto Farad accuracy during an overnight run. With a similar runtime using a multicore distributed processing capability, Raphael NXT technology provides fast 3D capacitance extraction on designs with 10k or more nets to high absolute accuracy – typically within 1% of a silicon reference design.
Silicon-accurate modeling of new parasitic effects, particularly device parasitics, is more important than ever as designers implement sensitive custom circuits in advanced process nodes. MOS device parasitics, such as gate-to-contact and gate-to-diffusion capacitances, are becoming ‘context-specific’ or layout-dependent, which has a pronounced impact on performance. Designers can no longer be sure that the parasitics for all instances of the same component will be the same. Identical transistors will have different parasitic effects depending on their physical location in the design. StarRC Custom’s gold standard extraction technology offers advanced modeling of context-specific device parasitics with atto-farad accuracy to reduce risk for designers.
Tuned Extraction for Simulation Performance
As process geometries become smaller and designs become larger, design teams need to achieve higher simulation productivity if they are to keep project schedules on track. An optimized link with Synopsys’ CustomSim unified custom simulation environment allows StarRC Custom to improve simulation runtimes and overall productivity.
Compared to simulation, parasitic extraction accounts for a relatively small part of a chip project. However, the quality of parasitic data that the simulator uses can have a dramatic effect on the time that a design team spends simulating.
StarRC Custom generates a highly optimized parasitic netlist that can help designers simulate faster without compromising accuracy. StarRC Custom offers advanced techniques to optimize extraction or parasitic netlist to accelerate simulation performance. Three specific techniques are described below:
- Selective device parasitic extraction: Performing context-specific device extraction boosts accuracy, but applied universally (full extraction) will produce unmanageable amounts of parasitic data that the simulator has to then manage. Selective device parasitic extraction allows designers to extract only those parasitic values that are meaningful to accuracy. They can selectively retain the device capacitances that impact circuit performance while grounding all other coupling capacitances and power net parasitics. Applying this to real customer designs has achieved 8 – 10x speed-up in performance with only 1–2% change in calculated delay.
- Active node (critical net) extraction. When a design is operational, only some of the nets may be active, and only for some of the time. Designers performing post-layout simulation may be sacrificing performance by extracting all nets in the design and passing full parasitics information to downstream simulators, even though only a fraction of the nets may actually impact timing or accuracy.
Pre-simulation runs can identify the most important active nodes, which StarRC can take in and use to select nets for extraction. Extracting only the active nets and their dominant coupling neighbors significantly reduces the runtime and netlist size, while guaranteeing accuracy on each extracted net. Using StarRC’s active node back-annotation flow with CustomSim can provide a further 10x simulation speed-up on large transistor-level designs. When applied to very regular designs, such as memory blocks, the speed-up can be as high as 100x.
- Hierarchical back-annotation simulation. Fully hierarchical methodologies can accelerate the chip development flow by allowing designers to continue to work with smaller blocks rather than the whole chip. However, hierarchical extraction may compromise accuracy if the extraction tools ignore parasitic information outside of a hierarchical block that might impact the structures within it.
CustomSim takes advantage of natural design hierarchy to provide the highest efficiency simulation. CustomSim’s advanced isomorphic hierarchical back-annotation technology allows designers to easily annotate the post-layout parasitics onto the pre-layout schematic netlist. Combined with the flat extraction parasitics from StarRC, this offers the most effective flow to achieve the dual goals of higher simulation performance and signoff accuracy. StarRC’s flat extraction technology accounts for all neighboring net coupling capacitances as well as thickness and width variation effects that are essential for signoff accuracy. On the other hand, hierarchical back-annotation technology of CustomSim provides the maximum annotation of the detailed parasitics while preserving the design hierarchy.
'In-design' Integration with Custom Designer
Custom design engineers work differently from other chip designers. They often need to make decisions ‘on the fly’ about cell sizing, the width and length of transistors and many other parameters. Typically, they want to interact with their designs, constantly iterating between creating and analyzing, and that requires an interactive, integrated flow.
Synopsys has built the Custom Designer environment natively on the OpenAccess database, offering the industry’s most productive and open custom implementation solution. It enables many interactive features. Designers can perform interactive post-layout analysis of their custom designs from a single cockpit, which allows them to perform ‘in-design’ analysis, extract the design and create an Open Access parasitic view. StarRC Custom has a seamless integration with Galaxy Custom Designer enabling post-layout analysis of custom designs in an interactive design environment.
Designing interactively means that designers are constantly jumping between a schematic view and a layout view. Designers want to be able to see the parasitic on certain nets in the layout view, then simulate and debug them. Intuitive probing capabilities allow designers to easily probe parasitics within the parasitic view or within the matching schematic view for design debug.
Performing tasks like accurate IR drop analysis requires the use of multiple applications. Typically, designers must extract the parasitics that are optimized for power-ground simulation and analysis, then view any problems in the layout, and finally fine-tune the design by performing what-if analysis to debug the problem. Synopsys in-design analysis capability allows designers to work this way by synchronizing data between CustomSim, StarRC Custom and Custom Designer.
Overall, StarRC Custom’s accurate parasitic extraction, combined with its direct links with CustomSim and Custom Designer, provides a complete infrastructure for custom IC designers to achieve faster convergence and increased design confidence.
StarRC Custom lets designers characterize both large and small custom analog blocks at transistor level and achieve the highest levels of accuracy with tuned simulation performance. It is a solution for next-generation custom design, part of Synopsys’ growing custom design tool portfolio that encompasses schematic design, simulation, analysis and physical verification.
The technology within StarRC is production-proven, benefiting from the core Star-RCXT technology and its broad existing qualification and usage. More than 40 leading semiconductor companies have already used Star-RCXT to implement hundreds of designs at 40/45nm process nodes with 16 foundries.
StarRC Custom is the foundation product in Synopsys’ expanded extraction suite, which also offers StarRC, architected for full-chip transistor-level and gate-level design, and StarRC Ultra, architected for advanced analysis flows, including statistical analysis. As process variation increases and design margins shrink, designers are using more modes and corners in their analyses to ensure maximum signoff certainty. The next-generation StarRC and StarRC Ultra solutions offer versatile solutions for full-chip, gate-level and transistor-level designs at leading-edge process nodes.
Figure 3. StarRC Extraction Suite
- StarRC Custom lets designers characterize both large and small custom analog blocks at transistor level and achieve the highest levels of accuracy. It is a solution for next-generation custom design, part of Synopsys’ growing custom design tool portfolio that encompasses schematic design, simulation, analysis and physical verification.
- StarRC provides full-chip transistor- and gate-level extraction for large analog and custom digital blocks.
- StarRC Ultra is the most advanced solution. It allows designers to cope with increased variation across processes (a problem at 45nm and below), using statistical solutions such as Monte Carlo simulation. StarRC Ultra also answers designers’ needs for emerging technologies including 3D stacked dies that use through-silicon vias (TSV).
Shekhar Kapoor is senior product marketing manager for parasitic extraction signoff products at Synopsys. He has 15 years of experience in semiconductor and EDA industries in design engineering and marketing positions. He holds an MS in Electrical and Computer Engineering from Virginia Tech and an MBA from Haas School of Business, University of California, Berkeley.
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