| Industry Insight|
New Technology Reduces Total Cost of Design
In his keynote speech to the San Jose Synopsys User Group, Dr. Aart de Geus, Synopsys Chairman and CEO, presented Synopsys’ R&D focus and the new technologies that are addressing the key issues of total cost of design and project schedule. In part two of a two-part article, Synopsys Insight reports the highlights from the speech.
There are some key trends that inform and guide the product changes and improvements that Synopsys is making to reduce total cost of design and improve productivity.
Foremost, chip development is no longer just about hardware. Designers must consider software at the outset. They can save time by working together to integrate hardware and software, and by verifying it together or in parallel.
But verification is no easy matter: designs are bigger and more complex, and the verification environment must consider analog and digital hardware, as well as software.
Synopsys’ verification team has added new features and capabilities to its traditional hardware verification tool set. Over the last five years, it has integrated simulation with other key technologies:
- testbench creation
- assertion checking
- coverage metrics
This year, the team has focused on improving speed, where possible exploiting multicore compute infrastructures. By partitioning both the design and the application for use with multicore technology, it is possible to achieve faster, better and more comprehensive simulation.
Many of today’s designs involve schemes for managing power that put new demands on simulation. MVSIM is a voltage-aware simulation engine that Synopsys has integrated with VCS®. It verifies designs with multiple voltage regions as they switch on and off. As well as developing low power verification technology, Synopsys has worked with ARM and its other partners on low power methodologies, and captured this knowledge in the Verification Methodology Manual for Low Power.
Unifying digital and analog simulation in CustomSim™ with VCS improves chip designers’ ability to address a broad set of design challenges incorporating high-speed digital and sophisticated analog, with much faster runtimes than in the past.
The Big Picture: Software
It is because embedded software offers so many compelling benefits that it plays an increasingly important part in electronic products today. Companies can adapt it to launch derivative products and, using software upgrades to solve bugs, can reduce development risk. Embedded software significantly enhances products – take the iPhone ‘Apps’, for example.
In addition to helping traditional hardware engineers, much of Synopsys’ development effort enables hardware and software engineers to work together to bring products to market faster.
The Software-Hardware Interface
Synopsys’ investments in the last two years have focused on the software-hardware interface. The company acquired Virtio to deliver a high-level software modeling capability, and then Synplicity and ProDesign’s CHIPit business unit, which between them delivered hardware and rapid prototyping technology.
Synopsys sees modeling, prototyping and systematic IP reuse as key practices in supporting engineers at the hardware-software interface:
- Virtual prototyping allows engineers to create a high-level software model so they can start developing code before the RTL is available, typically 9-12 months early.
- Rapid prototyping allows engineers to create a prototype using FPGA boards that run faster and with more detail than other models. Synopsys’ Confirma™ Rapid Prototyping Platform lets designers use FPGA-based prototypes to improve their time to market and avoid respins.
- IP has evolved to allow designers to quickly create multiple representations of their designs at multiple levels – for example, the functional design and its verification environment. Extensive use of IP allows design teams to focus their talent on differentiated parts of the chip.
Figure 1. System Prototyping: The Next Wave
Synopsys has primarily focused its IP development on interface IP – the communication blocks. The key trend in interface IP is speed. The demand for mobile video, for example, is driving specifications like USB 3.0. Synopsys is able to provide the host control, device controller and the PHY for USB 3.0, as well as software and a verification environment.
Synopsys is moving towards providing a state-of-the-art verification environment that sits between hardware and software, and manages multiple levels of abstraction while incorporating IP from both itself and its partners.
Design: Faster Closure
Galaxy™ is the Synopsys design platform that brings together designers’ core digital design tools: Design Compiler®, IC Compiler, PrimeTime® and, more recently, Custom Designer. The Synopsys development team is focusing on enhancing the tools to achieve faster closure – timing, power and the other electrical checks needed. The key here is not just, ‘How good are the tools?’ It is also, ‘How well do they work together?’
The answer to this is that Synopsys has made progress year on year. Synopsys first added a very fast placement capability to Design Compiler so that it could look ahead to anticipate timing delays. Then it added the capability to predict and minimize congestion. Now Galaxy performs multi-mode, multi-corner optimizations early in the flow. Systemic development of closer ties between Design
Compiler, IC Compiler, Custom Designer, StarRC™ and Hercules™, has enabled designers to look ahead and predict and remedy issues before they occur, which has a material impact on the overall design time.
Figure 2. Galaxy: Unified Solution for Custom and Cell Based Designs
Design Compiler and IC Compiler work together to enable designers to manage power throughout the design flow. But other products need to stay in tune with any changes to these key tools. For example, each time that the development team introduces new optimizations into Design Compiler and IC Compiler, they need to ensure that they optimize equivalency checking also. As well as accommodating new power optimizations throughout the flow, the same is true for all aspects of test pattern generation.
The Big Picture: Design Flow
Synopsys has made significant progress in improving individual tools and the way they work together. But the bigger picture is the design flow, and that’s why Synopsys has introduced Lynx Design System, a production-ready IC development platform.
Synopsys’ professional services group has been using previous versions of Lynx for a number of years, so this is the result of many years work and as a result it is tapeout-proven.
Lynx Design System is an open environment that supports third-party tools, libraries, and foundries. It includes validated IP, libraries and foundry technology data to accelerate project start. The GUI-based runtime environment simplifies flow configuration, execution, and monitoring, while process-specific tapeout checks and settings improve the quality of foundry handoff.
Figure 3. Lynx Design System
Lynx includes a web-based Management Cockpit that delivers visibility into key design metrics and trends to enable project transparency at all levels. Its Runtime Manager also allows designers to evaluate multiple design scenarios in parallel and its Management Cockpit shows them the results in a simple dashboard.
The standout benefit of Lynx is the way that it enables design teams to systematically capture their learning and improve the design flow. This will make design more productive and predictable, and will lower support costs for the methodology.
Future Bright for Technology
The industry is currently under enormous stress, and can expect to be for the next 12-24 months. That’s one of the reasons why Synopsys is interacting with partners and focusing on how it can help to reduce design costs and increase efficiency.
There are many growth areas for the industry: medical, the Internet, the role of embedded software… The future is bright for technology in general, and silicon technology will take a central role. Synopsys is continuing to invest in R&D and support and is now in a position where it can move forward even faster.
Aart de Geus
Since co-founding Synopsys in 1986, Dr. Aart de Geus has expanded Synopsys from a start-up synthesis enterprise to a world leader in electronic design automation (EDA). As a technology visionary, he is frequently asked to speak on topics related to the electronics industry. As one of the leading experts on logic simulation and logic synthesis, Dr. de Geus was made a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) in January 1999. He was also honored for pioneering the commercial logic synthesis market by being named the third recipient ever to receive the IEEE Circuits and Systems Society Industrial Pioneer Award. In 2002, shortly after transacting the largest merger in EDA history, Dr. de Geus was named CEO of the Year by Electronic Business magazine; and in 2004, Entrepreneur of the Year in IT for Northern California by Ernst & Young. In November 2005, Electronic Business magazine chose Dr. de Geus as one of "The 10 Most Influential Executives." Dr. de Geus is active in the business community as a member of the board of the Silicon Valley Leadership Group (SVLG), TechNet, the Fabless Semiconductor Association (FSA), and as Chairman of the Electronic Design Automation Consortium (EDAC). He is also heavily involved in education for the next generation, having created in 1999 the Synopsys Outreach Foundation, which promotes project-based science and math learning throughout Silicon Valley.
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