Synopsys at DATE 2008|
10 – 14 March 2008
International Congress Center, Munich
It is almost here – Europe's foremost conference and exhibition for electronic system design and test is on its way. With the industry split between those holding at 90 nanometers and above, and those rushing to 65 nanometers and beyond, the common denominator is the quest for more productive and yet predictable design solutions, to relieve the burden of the increasing engineering cost and effort– DATE brings all the latest solutions under one roof.
At stand A2 Synopsys will be showcasing products and solutions that help the leading innovators of the technological world to design the chip inside and ensure predictable success. Visit Synopsys at International Congress Center in Munich from 10 to 14 March and keep pace with the latest advances in design and verification, including:
- Eclypse Low Power Solution
DATE 08 gives visitors a chance to learn about the newly announced Eclypse Low Power Solution, the industry's most comprehensive suite of proven tools, IP, methodologies and services. Eclypse aligns Synopsys' proven offerings into a new, streamlined, easy-to-use low power workflow based around the Unified Power Format low power industry standard. It enables design teams to adopt advanced low power techniques while boosting productivity, reducing risk and ultimately delivering high-quality silicon that meets or beats power objectives.
- System-to-Silicon Verification
Visitors at DATE will be able to find out about Synopsys' proven system-to-silicon verification solution – the most comprehensive in the industry – and how it shortens time-to-market, raises productivity and increases predictability of chip verification, simplifying the process of deploying advanced system-level, functional and AMS verification methodologies.
- DesignWare® Intellectual Property
Astute chip design teams will be interested in learning more about Synopsys' DesignWare IP. There are significant benefits for those who use reliable high-quality IP from a single provider. Synopsys' broad portfolio includes complete IP solutions for controllers, PHY and VIP, and is complemented by comprehensive technical support.
At DATE 2008, Synopsys' suite demonstrations will include:
Ensure First Pass Success with Mixed-Signal Verification
Complex SOCs are mixed-signal in nature and in order to ensure first pass success it is essential to adopt a full chip mixed-signal verification methodology. Maintaining high verification coverage while simulating some blocks at the transistor level demands a mixed-signal verification solution that incorporates world-class production proven FastSPICE simulation technology. As part of Synopsys' comprehensive circuit simulation solution, the XA Acceleration technology delivers a new level of ease-of-use, out-of-box accuracy and performance to complement HSIM® and NanoSim®. With Discovery AMS, HSIM and NanoSim are tightly integrated with Synopsys' VCS® through direct-kernel integration. Multiple levels of abstraction are supported in addition to a unified debug environment.
The Common Platform 65nm and 90nm Design Enablement Ecosystem: One Design, Worldwide Multiple Sourcing
This presentation explores the benefits of the Common Platform 65nm and 90nm process technologies and design enablement ecosystem provided as part of the alliance by Chartered Semiconductor Manufacturing, IBM, and Samsung. This combined with the Synopsys reference flow and IP offers a complete, low-risk path to high-volume, low-power silicon with a built-in multi-sourcing capability. The proven, no-charge Synopsys reference flow includes support for the complete range of RTL-to-GDSII implementation tools, including advanced 65nm capabilities in IC Compiler. Advanced IP, including the first 65nm PCI Express PHY to pass PCI 1.1 compliance testing and the first multi-foundry, single-GDSII PHY to be Hi-Speed USB 2.0 and Hi-Speed USB On-The-Go (OTG) certified by the USB-IF.
Design for Manufacturing and Yield
Once an afterthought, yield has become an explicit concern in the advanced IC design process. Synopsys provides a complete DFM/Y solution that spans from TCAD to physical design and verification. Come see how TCAD brings process information into designers' hands to address CMP, litho and stress effects at the device level, and how IC Compiler and PrimeYield improve manufacturability and yield while respecting other design goals.
Integrating Design and Process: TSMC Reference Flow for 45nm Design Success
In this session, TSMC will provide an in-depth overview of their initiative for low power, 45nm designs and reducing time to market. With the introduction of TSMC Reference Flow 8.0SM and silicon-proven TSMC libraries, TSMC will share how they address key 45nm design issues such as power reduction, power integrity, statistical timing analysis, and Design for Manufacturing (DFM), based on the industry leading EDA methodologies and the Galaxy Design Platform from Synopsys.
IC Compiler 2007.12 Concurrent Hierarchical Design
With IC Compiler 2007.12, Synopsys introduces Concurrent Hierarchical Design. Historically, design tools have relied on a "plan-then-implement" flow. Concurrent Hierarchical Design transcends these flows enabling a concurrent methodology that seamlessly blends planning and implementation tasks while offering an integrated environment with a single timer and a high degree of correlation to sign-off. IC Compiler provides hand-crafted quality macro placement, intelligent power network support, and MinChip technology for automatic die-size reduction all on a single timer foundation that enables faster time to closure and higher quality of results.
Functional Verification with VCS
This presentation will highlight new technologies in the VCS Functional Verification Solution and new applications in the industry-leading de facto standard VMM verification methodology for SystemVerilog. It will demonstrate the powerful bug-finding technologies, comprehensive coverage capabilities, and new innovative coverage convergence techniques available in VCS MX. It will also highlight new VMM Applications such as Register Abstraction Layer, Hardware Abstraction Layers and more, as well as illustrating new, innovative low power verification techniques that can be applied to multi-voltage designs. These techniques are used to find functional design bugs related to low power specification, early in the product development cycle.
Galaxy Platform for Synthesis and Test: Predictable Success in Record Time
Those who attend this presentation will learn how using Design Compiler® topographical technology can help designers to finish designs faster. In addition to exploring the latest enhancements to the Design Compiler product family, Synopsys will give its audience a sneak preview of a new breakthrough in synthesis technology: congestion predictions and optimizations in synthesis. For test, Synopsys will highlight power management in DFT MAX scan compression and TetraMAX® ATPG, and demonstrate how its new timing-aware pattern generation capability can significantly improve test quality over standard at-speed testing.
Advances in Analysis and Signoff to Meet the Demands of 45nm Design
With 45nm processes moving to mainstream availability, designers want to understand the implications of the new processes on their signoff flow. This presentation will review the improvements in performance and accuracy being delivered by PrimeTime® and CCS libraries to meet the demands of 45nm design.
Automotive Electronic Solutions
The automotive electronics that are rapidly being developed, refined, and deployed in today's vehicles are driven by the high demand in the marketplace for safety, infotainment, and emissions control. Implementing reliable electronic systems is a challenge across the supply chain from ICs, embedded software, and mechatronic systems. This session will illustrate how Synopsys is addressing the design needs from chip to system in order to improve reliability, increase performance and reduce costs.
Synopsys Eclypse Low Power Solution
Power has become an increasingly critical issue for the semiconductor industry, not only for traditionally power-conscious applications such as wireless, mobile, and consumer electronics, but also for high performance applications that are now expected to meet energy conservation requirements. This session will cover Synopsys' low power solution – a comprehensive, holistic approach to low power, where design and verification operate from a common, consistent basis for defining power intent. It will include a UPF-based demo of the end-to-end flow.
Low Power Implementation with UPF: ARM Cortex M3 Case Study
Techniques such as MTCMOS based power gating with state retention can yield significant reductions in the standby power consumption of a design. The Unified Power Format (UPF) provides designers with a common, interoperable format for specifying low-power intent across the design implementation and verification flow. This session takes the designer through a basic implementation and verification flow illustrating the use of UPF, followed by a case study of a UPF based low power implementation of the Corte M3 processor from ARM.
Integrating Synopsys DesignWare IP into SoC Designs
This interactive session will uncover how to successfully deploy high-quality DesignWare IP into system-on-chip designs. It will discuss the latest IP products, features and standards that are being implemented into a wide variety of applications. Visitors will find out how the complete, silicon-proven DesignWare IP solutions consisting of digital controllers, mixed signal PHY IP and verification IP can help to reduce integration risk and speed design time.
System-to-Silicon Verification Solutions
Chip verification has traditionally been an afterthought in the design process, or the domain of small team of technical experts. Today, with verification dominating chip development schedules and budgets, senior executives at IC and systems firms are focusing on the business impact of the chip verification process. This session will review how Synopsys' comprehensive system-to-silicon verification solution can be used to improve verification schedule, cost and risk.
Complete System Verification Using Virtual Platforms
Virtual platforms have proven to be a powerful solution for pre-silicon software development. Early availability of a virtual platform plus the associated system software allows for additional use cases, including RTL verification in a complete system context. Visitors will learn how functional models, coming from their algorithm designers, seamlessly integrate into their virtual platform, enabling early platform availability. They will also learn how RTL components/subsystems can be analyzed within a virtual platform setup, running real system software.
Visit Synopsys at stand A2
ICM, Munich, Germany
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