| Partner Solution|
New Differentiated Embedded Memory IP Enables Higher
Performance and More Cost Effective, Power-Efficient SoCs
In many of today's SoC designs, embedded memory accounts for well over half of the transistors on a chip. With growing demands on performance, memory implementation can now make or break a design. Christophe Berteau-Pavy, Synopsys, and Dr. Esin Terzioglu, Novelics, explain how the companies have collaborated to deliver new silicon-proven DesignWare® embedded memory IP that will enable the design and manufacturing of higher performance and more cost effective, power-efficient SoCs.
With the increased feature and content requirements in today's consumer electronics applications, it is easy to see why the need for on-chip memory is growing so rapidly. Higher resolution displays, advanced 3D graphics, streaming video and higher quality audio are just some of the typical features that require 'byte loads' of high-performance, low power embedded memory (Figure 1).
Figure 1. Embedded memory dominates chip area
Source: Semico Research Corp. – ASIC IP report; 2007
Furthermore, the mean design clock frequency, currently around 540MHz, is also increasing at around 25 percent per year according to data collected at the Synopsys Users Group event in 2008. In order to address the need for higher performance and more power efficient SoCs, Synopsys offers two distinct embedded memory IP solutions. The high density DesignWare coolSRAM-1T™ IP enables designers to incorporate more system memory on-chip compared to a standard 6T-SRAM, thus lowering power and overall system cost. The DesignWare coolSRAM™ family addresses the need for ultra low power and high performance design implementations. So, whether it is lowering manufacturing costs, lowering power or increasing performance, Synopsys has an embedded memory IP offering to meet the specific design requirements.
Cost Effective, High Density SRAM-1T Memory IP
There are many benefits of using high-density embedded memory. For example, if half of the total chip consists of memory, using memory that is twice as dense will reduce the total die area by up to 25 percent. On-chip memory is intrinsically more power-efficient than off-chip memory and increasing the amount of embedded memory reduces power-hungry IO transitions. The DesignWare coolSRAM-1T is an innovative single-transistor embedded memory IP that offers twice the density of standard six-transistor SRAM memory. Leveraging Novelics' 1 Transistor + 1 Capacitor bitcell, the DesignWare coolSRAM-1T is implemented in unmodified bulk logic CMOS process and does not require additional manufacturing costs or processing steps. Unlike other single-transistor approaches, this unique implementation provides designers with a true zero-added-cost solution, offering 15 percent or more reduction in manufacturing costs compared to existing SRAM-1T products.
Other single-transistor solutions today cannot be implemented on standard logic CMOS and require additional manufacturing masks and/or processing steps, which typically adds around 15 percent to the wafer manufacturing costs. This wafer cost penalty makes the single-transistor SRAM economically viable only for designs with very large amounts of memory. The deviation from the standard CMOS process also increases manufacturing risks and can potentially reduce overall yield. Figure 2 shows that competing 1T memories are only more cost-effective than standard 6T memories when more than 12Mb of memory is required. Because the DesignWare coolSRAM-1T incurs no additional manufacturing cost it is a more cost-effective alternative to competing 1T memories and can provide significant area gains compared to 6T for even small (128Kb) amounts of memory.
Figure 2. Cost comparisons for different embedded memory solutions
High Performance and Low Power Standard SRAM Memory IP
Today's designers face the daunting challenge of meeting very high levels of performance and functionality integration while trying to reduce overall system level power consumption, thus creating the need for high performance and low power standard SRAM architectures.
The DesignWare coolSRAM memory IP family offers low power, high-performance standard SRAMs including single port 6T, dual port 8T register file and ultra high-density ROM. The DesignWare coolSRAM IP reduces dynamic power consumption by up to 50 percent compared to other SRAM-6T offerings. It is also designed for high performance, enabling implementation of a 32Kb cache memory system operating at speeds over 1.2GHz on a leading 65nm low power process while drawing less than 6µW/MHz.
Leakage power emerged as a major issue with the transition from 130nm to more advanced technologies. Current leakage gets worse with each new process node and for deep-submicron technologies over half of the total power consumption can be due to leakage.
The DesignWare coolSRAM IP architecture (Figure 3) is optimized for low dynamic power and also includes optional leakage control features, detailed below, which combine to achieve 10 times lower leakage compared to other memory technologies.
With leakage control features enabled, each block in the memory cell array is either in a very low leakage active mode or an ultra low leakage sleep mode.
The very low leakage active mode is implemented with patented source biasing circuitry which automatically minimizes leakage current within the memory cell arrays not being addressed. This is completely transparent to the user and requires no system level control logic.
Figure 3. DesignWare coolSRAM architecture
For further reduction in leakage current, each individual memory block (or bank) in a memory instance can be independently shut down and put in a sleep mode which results in virtually zero leakage. This provides an increased level of granularity for power management at the system level and is controlled through an extremely simple user interface.
In addition to the very low leakage active mode and block-level sleep control, the header and footer devices incorporate transistors with longer channel lengths in peripheral blocks such as the decoder and control circuits, which further reduces leakage.
The DesignWare coolSRAM-1T IP further reduces power by allowing a single bit or single byte write to memory.
The DesignWare coolSRAM-1T and DesignWare coolSRAM memories are designed using a simple unified web-based memory compiler (Figure 4) that generates the exact memory configuration required. Designers specify address depth, word width and select optional features such as leakage control, subword capability or redundancy. The compiler generates all possible memory cuts and topologies based on all valid multiplexing and banking options conforming to the user inputs. The different memory cuts and their key performance characteristics are then conveniently displayed in a table which can be re-ordered by the user based on design priority. This enables the user to select the best fitting memory instance across all axes of performance.
Figure 4. Web-based memory compiler interface
Figure 5. Compiler memory selection options
Newport Media is a fabless semiconductor company that develops and sells highly integrated solutions for emerging digital audio and mobile TV broadcast products. The company's latest and most advanced designs implement coolSRAM-6T (29 instances) and coolSRAM-1T (five instances) embedded memory IP. The benefits are clear, with memory area down by 50 percent and memory power reduced by 65 percent compared with previous implementations.
"We have been able to reduce our overall power consumption and silicon area significantly and are shipping in volume. We are looking forward to the future developments on the coolSRAM and coolSRAM-IT technology driven by Synopsys and Novelics."
Mohy Abdelgany, chief executive officer, Newport Media
With over half of a typical design now comprising on-chip memory, using memory IP that is optimized for area, power and performance offers significant benefits for the entire SoC.
High-density SRAM-1T memory IP enables integration of up to two times more memory than a standard 6T-SRAM on advanced technology nodes, enabling chips to incorporate more system memory on-chip, thus lowering power and overall system cost. The DesignWare coolSRAM-1T is implemented on a bulk logic CMOS process and does not require additional masks or manufacturing steps. This implementation provides designers with a true zero-added-cost solution, offering up to 15 percent reduction in manufacturing costs compared to existing single-transistor memory IP products.
Unlike competitive solutions, the DesignWare coolSRAM-1T memory IP is a compiler-based solution providing designers with immediate access to the specific memory IP instance they need without any compromise on instance storage capacity or topology. The combination of not having to pay a premium on wafer price coupled with the flexibility of the compiler-based technology enables designers to reduce system-level power and cost, even for designs with small amounts of memory.
For standard Single Port, Dual Port or Register File SRAMs, the advanced power control modes and high performance architecture of the DesignWare coolSRAM family of embedded memory products enable designers to develop smaller and faster SoCs that are also highly power-efficient.
The ongoing collaboration between Synopsys and Novelics ensures state of the art characterization and quality assurance processes to provide the highest quality design and deliverables.
Esin Terzioglu, Ph.D.
Chief Technology Officer and Co-Founder of Novelics
Novelics co-founder Esin Terzioglu serves as chief technology officer for the company, overseeing technical strategy, hiring and organization. Dr. Terzioglu is responsible for managing the engineering projects and innovations for the company's embedded memory technologies. Prior to co-founding Novelics, Dr. Terzioglu held key technical positions at Broadcom Corporation from 1999 to 2005, progressing from staff scientist to principal scientist. He led the development of four generations of embedded SRAM memory technology, contributing to industry-leading achievements in memory area efficiency, power and speed. Dr. Terzioglu has published 11 technical papers in the areas of fabrication processes, device physics and superconducting electronics, and holds more than 50 patents, mainly in circuit design and semiconductor memory technologies. Dr. Terzioglu received his bachelor's of science in electrical engineering from the University of Rochester, his master's of science and his Ph.D. in electrical engineering from Stanford University with a minor in computer science.
Product Marketing Manager at Synopsys
Christophe Berteau-Pavy joined Synopsys in 1998. In his current position, Christophe is responsible for our embedded memory IP product line as well as managing distribution of foundation IP from foundry partners. He has handled multiple product lines in the Synopsys DesignWare IP portfolio over his 10 years with the company. Prior to joining Synopsys Christophe held R&D positions at LSI Logic and Thomson and worked on system level verification and ASIC design methodology. Christophe holds a BSEE from the EFREI engineering school in Paris.
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