| Technology Update|
Multi-core Support Accelerates TTR
Multi-core technology has the potential to speed up many chip design activities including design, verification, implementation and manufacturing. As Synopsys’ Steve Smith explains, providing broad support across multiple EDA tools takes a tailored approach that depends on the exact needs of the application.
Today’s designs require more effort, analysis and verification than ever. Design complexity is increasing: shrinking technology yields more features on a chip and more chips on a wafer. Managing this design complexity requires extra synthesis and simulation and involves ever-increasing volumes of data. But increasing design size isn’t the only thing that puts pressure on the EDA environment: finer feature sizes demand advanced manufacturing processes, which now require more sophisticated design rule checking, optical proximity correction (OPC) and yield diagnostics.
The shifting economics of chip design have always influenced the makeup of the design environment. For example, the cost of manufacturing a design error is now prohibitive and for that reason design teams are investing in EDA environments that support 'correct by design' development. Essentially this means more tools, more built-in test logic, and more post-layout simulation. All of these requirements put pressure on the entire environment – not just on the tools and teams, but also on the compute infrastructure.
Taking all of these issues into account, Synopsys estimates that the shift from 65nm design to 45nm technologies will increase compute demand for design and manufacturing tasks by a factor of 10. While increased investment in compute servers is required to handle the growing processing demands, the need to invest a greater amount in power and cooling facilities compounds the cost of the overall compute infrastructure. According to a 2006 IDC report, the cost of power and cooling now outweighs the cost of the servers themselves.
The New Landscape of Parallel Computing
Endlessly increasing the clock frequency of a single-core processor is no longer a viable solution to meet the needs of performance-hungry applications. Instead, multi-core processing is at the heart of the new conventional wisdom for computers.
While multi-core processing can dramatically improve software performance for end users, for EDA developers it presents new challenges for designing and implementing applications. Unfortunately there is no ‘one size fits all’ approach. Deciding whether to employ multi-threading, parallel processing, distributed processing, partitioning or pipelining really depends on the profile of the application and its compute, memory, latency and storage needs.
Synopsys’ multi-core initiative aims to help design teams maximize the throughput of their multi-core compute infrastructure and therefore reduce time to results. Multi-core technology is not new for Synopsys. For example, Synopsys’ VCS® functional verification solution with native testbench technology is widely deployed in compute farms, enabling faster and more predictable chip verification. Another established multi-core compliant product, Synopsys’ Proteus lithography solution, offers near-linear scalability using multiple processors. Figure 1 shows the breadth of multi-core support for Synopsys’ tools today.
Figure 1. Synopsys Multi-core Solutions
Static timing suits a distributed approach. Synopsys’ PrimeTime®’s distributed multi-scenario analysis feature allows design teams to perform several static timing analysis runs to verify in parallel all of a design’s modes and operating corners. The scenarios are automatically distributed onto the target computers and the results are merged together to enable easier analysis.
For many design teams, the move to smaller geometries necessitates accurate transistor-level simulation with post-layout parasitics. Enhancements to Synopsys’ HSPICE®, including improvements to the core engine and new multi-threading capabilities, boost performance and speed circuit simulation for complex analog and mixed-signal designs. As a result, circuit designers can now run HSPICE simulations up to three times faster on single-core processors and up to six times faster on four-core processors, compared to the 2007.09 release of HSPICE.
HSPICE multi-threading capabilities allow engineers to accelerate simulation of large analog designs with full layout parasitic effects. As a result, it takes just hours instead of days to simulate fully extracted post-layout designs.
In the traditional tapeout flow, mask synthesis precedes mask data preparation. Serial manufacturing flows need a complete post-OPC database before beginning mask data preparation.
Proteus Pipeline Technology
Figure 2. Proteus pipeline technology
Synopsys' Proteus Pipeline Technology (Figure 2) runs mask synthesis and mask data preparation concurrently. By deploying this capability across its portfolio of manufacturing tools, Synopsys provides customers with increased hardware efficiency, enabling significant reductions in both CPU memory use and manufacturing turnaround time.
Pipeline Technology uses parallel data processing that spreads the computational load evenly between CPUs. Applications such as reticle enhancement techniques, OPC, mask rule checking, lithography rule checking, mask data preparation, and user-customized geometry operations are executed concurrently. It is possible to drastically reduce memory footprint without needing to hold complete databases at any point.
The next phase of Proteus Pipeline Technology deployment will include incremental handoffs to the mask-write hardware. This will enable engineers to perform mask writing concurrently with all of the applications in the mask tapeout flow, further reducing the time to produce a mask.
Multi-core processing is central to the new conventional wisdom for computer technology. EDA applications must take full advantage of multi-core platforms for designers to truly benefit from the increased productivity that advanced design environments offer.
Synopsys provides a broad range of multi-core support across its Galaxy™ implementation, Discovery™ verification and DFM solutions. By profiling applications in terms of their compute, memory, latency and storage needs, Synopsys builds its tools on multi-core technology that will deliver the best performance for each application.
Senior Director, Product Platforms Marketing.
Steve Smith is responsible for Synopsys' product platform strategy and marketing campaigns. He is a ten-year veteran at Synopsys, including various functional verification and design implementation marketing roles. He has more than 25 years of experience in the EDA and computer industries, holding positions in both engineering, field applications and product marketing. Prior to Synopsys, Steve worked at Viewlogic Systems, Teradyne, Unisys and ICL. Steve holds a bachelors degree in Mathematics from Lancaster University, England.
©2008 Synopsys, Discovery, Formality, Galaxy, Hercules, HSPICE, PrimeTime, Sentaurus, Star-RCXT, TetraMAX and VCS are registered trademarks or trademarks of Synopsys, Inc. Any other trademarks or registered trademarks mentioned in this article are the intellectual property of their respective owners.