| Technology Update|
Automating Advanced Low Power Multi-Voltage Design
Low power design demands a coherent approach. Larry Vivolo, Director of Product Marketing and Josefina Hobbs, Technical Solutions Architect, both Synopsys, introduce the Eclypse™ Low Power Solution, and explain why the industry needs a comprehensive solution to automate advanced low power, multi-voltage design.
For certain sectors within the electronics industry, low power has always been a consideration – but not necessarily a limiting factor on design. Historically, saving power would rarely be at the expense of functionality or performance.
Balancing power against performance has traditionally been a strategic decision, made at the design stage and implemented at the component level. Use of this trade-off between power and performance to differentiate one product from a previous generation, or its competition, was common. This was possible because it was once relatively simple for integrated device manufacturers (IDMs) to offer low power implementations of complex devices. For them, low power could be achieved through a combination of their design team's skill and experience, and perhaps, more importantly, the inherent reduction in power as a result of shrinking process nodes.
However, with each subsequent move below the 180nm node, the inherent reduction in power that semiconductor fabrication once delivered has declined. The problem is that leakage current, in particular, has overtaken dynamic current consumption, due largely to the device characteristics of transistors operating at much lower voltages.
As transistor dimensions continue to shrink, the challenge of integrating them in higher numbers continues to increase. It is simply becoming nearly impossible to provide adequate current and heat dissipation for transistors packed so closely together. Choosing not to adopt a low power methodology, therefore, is a luxury that has all but disappeared.
Achieving low power design is now focusing the minds of everyone in the semiconductor supply chain. Effective low power design requires collaboration between design teams, IP vendors, and tool and solution providers. Only through implementing coherent methodologies, by making them available across the spectrum of tools that the supply chain relies on, can the industry really meet the ever-increasing challenges of low power design.
Low Power Techniques
Long before the power issue of leakage/static current became so prominent, IC designers were already encountering and overcoming the problems associated with dynamic power. There are two main components of dynamic power, the first one being the current consumed in the wires connecting all of the cells in a device. A signal is passed from one cell to the other by charging and discharging the capacitance on that interconnect, and every capacitive charge requires some amount of current to 'switch' its value. This is known as 'switching power'. The more activity that occurs on a given interconnect, the more switching power, and thus the more dynamic power, is consumed.
The second component of dynamic power consumption occurs inside the gate itself. It is relatively simple to appreciate that the more often a CMOS gate switches between states, the more the gate consumes current. This is the 'pay back' for the efficiency of CMOS in its quiescent state; current only really flows in a CMOS gate during a transition between 'on' and 'off', because in its quiescent state one of the transistors is always in its non-conducting state.
During a logical transition, both N and P type transistors in the gate must change state and for a small period of time both transistors will be conducting. This means that for a small period of time during every transition there is a low impedance path between the supply rail and the ground rail, which causes a surge of current to flow. The more frequent the logic transitions, therefore, the more frequent the surges and the higher the dynamic current. This is the 'short circuit' component of dynamic power.
In devices with reasonable transistor densities, operating at relatively low clock frequencies, these power surges were bearable. As densities and frequencies were pushed higher, they became more problematic.
To counteract these surges, engineers began to instigate complex clock gating schemes, which reduced unnecessary gate switching. This was followed by the more elegant technique of frequency scaling, which geared the clock frequency to demand; the higher the demand the faster the clock, thereby keeping transitions to a minimum. This began to echo the traditional power/performance trade-off applied at the component level and the next logical step was to apply the same kind of scaling method to the supply voltage, which returned even greater power savings.
Controlling Static Power
Just as the problem of dynamic power became more under control, the issue of static power arose. This occurs during the time when at least one of the transistors in a CMOS gate should be 'hard off' and not conducting. The problem revolves around the reduction in supply voltages associated with smaller geometries. The lower the voltage, the harder it becomes to drive transistors into their non-conductive state, resulting in a small amount of current flowing when none should be present; the so-called 'leakage' current. This is also referred to as 'static' power, since the current consumption occurs when the gate is in a non-transitioning 'steady' state.
There is an answer to this, which is to raise the threshold voltage at which the transistor switches. The penalty for that, however, is a slower switching transistor. Another solution is to disconnect the current path to large parts of a design when not needed, to reduce leakage current to zero for the parts that are shutdown. However, this, too, has its drawbacks, typically one of memory retention and 'reboot' times. The middle ground here again falls to the supply voltage, by implementing different power domains across a design. Using a lower voltage, where performance allows, reduces power consumption, while supplying a higher voltage where power is less crucial maintains performance. For the most power conscious designs, a combination of different operating voltages and power domain 'gating' is employed. This 'multi-voltage with shutdown' approach carries a significant design cost, but it is one that must be borne in order to create low power devices.
It follows, then, that combining multi-voltage with shutdown and dynamic voltage scaling can yield even more significant power savings. Today, to meet their power goals, designers must implement advanced low power design techniques comprising power gating, multi-voltage, and dynamic voltage-frequency scaling (DVFS), forcing a major shift in how engineers create and verify chips. However, due to the design complexity and a prior lack of EDA automation, engineering teams faced analyzing and implementing these techniques manually, with little assurance that they would meet power budgets without impacting performance.
Recently, Intel announced it had successfully manufactured a quad-core processor that integrates two billion transistors. Designing a two billion-transistor device could now become the norm, provided the optimization of that design for low power operation doesn't require a level of design effort that renders it uneconomical – exactly what the EDA industry aims to address. Without the necessary EDA tools to tackle the low power implementation and verification of complex designs, however, there is a real possibility of that happening.
The Synopsys Eclypse Low Power Solution
The traditional approach to this design problem relies too heavily on engineers manually applying low power techniques. The solution, therefore, is to automate this process, through a combination of leading-edge EDA tools and conformity to an industry-wide accepted low power standard.
Synopsys believes the Unified Power Format (UPF) offers a route to that solution. By adding UPF support to its range of design tools, Synopsys has created the industry's first comprehensive design environment that specifically targets a low power, multi-voltage design methodology, with a complete tool flow comprising RTL design, verification, RTL synthesis, test, physical implementation and sign-off. Figure 1 shows the key elements of the Synopsys Eclypse™ Low Power Solution.
Figure 1: UPF support throughout the Eclypse Low Power Solution
UPF is an HDL extension that allows power intent to be captured as part of the design semantics. Through commands such as: create_power_domain; set_domain_supply_net; create_supply_net and connect_supply_net, it provides a definition syntax for low power methodologies, describing the strategy for power distribution and signal isolation, as well as allowing design teams to set power requirements and constraints.
Implementing those methodologies requires support at the tool level, an awareness of the design constraints, and a voltage-aware verification methodology. The Eclypse Low Power Solution addresses these requirements.
Low Power Verification
As described above, the use of multi-level voltage domains can create significant challenges at the design stage, the effects of which must also be verified to validate functionality and avoid costly respins.
Existing verification solutions can't address this need for verification of the functional states in all of the power modes, as well as verification of power state transitions and sequences controlled by firmware. Without this level of visibility in to a multi-voltage design, a single unforeseen error could drive a device into an unknown state, cause lock-up or induce unpredictable behavior.
Synopsys' Multi-Voltage SIMulator (MVSIM) is an integral component of Eclypse, which can accurately simulate techniques such as dynamic voltage scaling, adaptive voltage scaling, power gating, retention and body bias. It includes support for ARM's own adaptive voltage scaling solution called 'Intelligent Energy Management' and co-simulates alongside an existing industry-standard RTL simulator.
MVSIM provides verification of low power techniques, including dynamic voltage and frequency scaling and low VDD standby, and understands the power intent as expressed by UPF, enabling verification of multi-voltage designs at RTL and at gate-level. It also supports voltage-aware modeling of voltage regulators, level shifters and power switches.
The overarching intent of the Eclypse Low Power Solution is that all its components work together towards a common pursuit. In addition to MVSIM, Eclypse includes MVRC (the static power aware rule checker); Design Compiler®; Power Compiler; IC Compiler; DFT MAX; Formality®, and PrimeTime® (key components of the Galaxy Design Platform). These are combined with additional tools for low power design, including Innovator; HSPICE®; HSIM®; NanoSim®; TetraMAX®, and PrimeRail, as well as DesignWare® IP, all backed up by the expertise of Synopsys Professional Services.
Advanced Low Power Technologies
The Eclypse Low Power Solution brings designers several new, advanced low power technologies. Automated generation and reporting of multi-voltage assertions dramatically improve the ease-of-use and reduce the risk in functional verification. Enhanced clock gating and low power clock-tree synthesis lets designers optimize their clock structures for low power while also achieving required skew and timing goals. Advanced multi-threshold leakage optimization, which constrains the ratio of low Vt cell area to total cell area, provides optimal leakage power recovery independent of a design's process corners. Enhanced automation for power switch insertion and optimization enables power planning exploration and 'what-if' analysis using IR drop and area constraints.
Core Eclypse components now support UPF and are compatible with the Low Power Methodology Manual (LPMM). Co-authored by Synopsys and ARM, the LPMM is a distillation of the experience of low power experts within ARM and Synopsys, forming a 'how to' guide to managing power in SOC designs.
As device features continue to shrink, operating at lower voltages, it will become necessary to develop IP that is inherently low power aware. DesignWare® IP is Synopsys' library of IP optimized for low power design, using a range of aggressive power management strategies. For IP providers implementing designs using advanced low power techniques such as multi-voltage and power gating, it will be necessary to provide customers with additional deliverables including a UPF file that contains the definition of the power connectivity and power behavior of the IP.
Delivering low power designs at 90nm, 65nm and 45nm is possible using the right methodologies and tools. With the introduction of the Eclypse Low Power Solution, Synopsys is taking the lead in delivering those critical technologies, enabling all SoC designers to implement proven low power techniques in a coherent, easy to adopt flow.
To learn more about the Eclypse Low Power Solution and low power design techniques, attend one of the free worldwide Synopsys Low Power seminars. To discuss low power issues, visit the Synopsys Open Community website at www.SynopsysOC.org.
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