| Technology Update|
IC Compiler with Concurrent Hierarchical Design
As designs migrate to smaller geometries, on-chip integration increases and design sizes mushroom, many designers are compelled to implement their designs hierarchically. Mark Bollar of Synopsys explains how IC Compiler, part of the Synopsys’ Galaxy™ Design Platform, delivers higher productivity to designers with its new Concurrent Hierarchical Design where planning and implementation occur in tandem.
Historically, physical designers have designed their chips using a “plan-then-implement” approach by creating a floorplan first and then completing the place and route tasks using a different tool or design environment. These "plan-then-implement" flows have worked well for simple designs. However, for complex designs, these flows lead to the late discovery of physical design issues, resulting in overdesign and often requiring costly iterations back to the early planning stages.
For these complex designs, a concurrent flow that seamlessly blends planning and implementation tasks and offers an integrated environment becomes increasingly critical. Not only is this the natural and intuitive approach designers need, it also results in an extremely predictable flow that delivers higher productivity and greater quality of results.
Flat and Hierarchical Design
Design teams decide whether to tackle chip implementation by maintaining the hierarchy or by flattening the design. There are pros and cons to both approaches. What’s important is that the design environment does not constrain the team’s decision – ideally physical implementation tools should allow a flexible design approach and support both flat and hierarchical design styles.
There are several reasons why designers now exploit design hierarchy in order to deliver working silicon on time. Design complexity is a major driving force in the move to hierarchical design. More of today’s designs are well over 4 million instances and contain complex IP blocks, including complete cores.
Use of hierarchy also allows design teams that are distributed around the world to easily share design tasks and better leverage computer resources for both design and verification. Taking a hierarchical ‘divide and conquer’ approach reduces the overall design runtime when compared to running a large flat design and is a major factor in improving overall design productivity, particularly for larger designs. While managing a hierarchical design typically presents more challenges than managing a flat design, hierarchy enables implementation of late design changes on a local block basis without disturbing the rest of the design.
Concurrent Hierarchical Design requires a number of advanced technologies to enable the productive development of complex chips. With this new approach, design planning progresses as an integrated activity that is naturally refined throughout the entire development process enabling the designer to make changes easily right up until design closure and tapeout.
A primary technology requirement for Concurrent Hierarchical Design is a single environment that uses best-in-class common engines that are physical hierarchy aware and a single timer throughout the entire physical implementation. (Figure 1) Achieving high quality of results is only possible when the best technology and optimization engines are deployed for key tasks such as planning, placement, clock tree synthesis, and routing. This common environment leads to accurate placement and congestion, IR-drop analysis, and timing correlation between design planning and detailed implementation providing predictable design closure.
Figure 1. Common engines must be shared throughout the design flow
Being able to handle designs at the top-level that include blocks at varying states of completion and at different levels of abstraction is another key capability that allows designers to work productively. The ability to intermix blocks that are at different levels of abstraction including black boxes, standard cells, soft macros, hard macros, and interface logic models (ILMs) gives the designer maximum flexibility in managing chip-level development. Adding to the flexibility, the common engines support choices of effort levels. Designers can apply low effort early in the development cycle when the design data is rough, and high effort as the data matures. Additionally, the engines are tolerant of many types of dirty data associated with early versions of design data.
Flexibility is a key requirement especially when it comes to support of multiple design styles. As well as support for flat and hierarchical design approaches, support for channeled and abutted layout styles and structured datapath designs offers designers the choice to pick the design style that is best suited for the chip architecture.
Low power design is a mainstream activity now and decisions taken during the planning phase of the design have a significant effect on the final power dissipation of the chip. Effective design planning must support innovative low-power design techniques such as automatic Power Network Synthesis (PNS) and Power Network Analysis (PNA) while at the same time be multi-voltage aware and include advanced MTCMOS power switch techniques.
A high degree of automation within the flow helps designers to finish design planning tasks quickly and accurately. Furthermore, automation allows the designer to explore the design space more effectively. For example, by automatically generating different floorplans driven by different placement constraints, the designer can easily select an initial floorplan that will deliver the best quality of results.
Best in class engines, flexibility, and a high degree of automation enable designers to identify and solve problems quickly and early in the development cycle. For example, finding and removing routing congestion within blocks resulting from the interaction of block pin, macro, and standard cell placements, or quickly adapting to block sizes that increase or decrease as design data matures, and ultimately insuring that precious silicon area required is minimized.
Key Features of IC Compiler’s Concurrent Hierarchical Design
IC Compiler is a complete physical implementation system and supports budgeting and floorplanning, top-level implementation, and block-level implementation. It includes everything necessary to implement next-generation designs including physical synthesis, flat and hierarchical design planning, placement, routing, timing, Signal Integrity (SI) optimization, power reduction, Design-For-Test (DFT), and yield optimization (Figure 2). IC Compiler has a unified, Tcl-based architecture that supports innovative features and harnesses some of the best Synopsys core technologies. With the latest release of IC Compiler, Synopsys enables a concurrent methodology where planning occurs in tandem with implementation delivering faster time to tapeout for both hierarchical and flat designs.
Figure 2. IC Compiler supports multiple design styles
Common Environment and Engines
IC Compiler uses a single timing engine for every timing task within the flow. This timing engine allows fast analysis for planning and accurate analysis at the detailed design stages where precision is required. Using the same underlying timing technology ensures predictability throughout the flow. In fact, the single timer in IC Compiler is the exact same timer used in Design Compiler® Ultra with topographical technology. Design Compiler Ultra also leverages IC Compiler’s placement technology ensuring fast, accurate synthesis that is tightly correlated with the final design. Besides sharing common synthesis technology, IC Compiler incorporates the same delay calculator as PrimeTime and has commonality at the algorithm level with both PrimeTime® and Star-RCXT™ extraction assuring sign-off quality implementation.
Common placement, optimization, clock tree synthesis, and routing engines in IC Compiler that are physical hierarchy aware ensure that the design is predictable and correlated throughout the flow. Designers can be confident proceeding with a given floorplan knowing that early design analysis results for placement, congestion, and timing during the design planning phase will correlate to the final implementation. Because of this predictability designers are able to make any needed changes earlier in the design cycle, therefore mitigating issues that come to light late in the detailed implementation phase when changes are extremely costly.
Use of a common GUI and Tcl for both planning and implementation within IC Compiler enables designers to easily explore and manipulate the design hierarchy, preview soft macros, and control their entire design from a single environment. Since IC Compiler has a single environment for design planning and detailed implementation, designers can read in SDC constraints once during implementation and all design data is stored in the industry standard Milkyway™ database.
Mixed Levels of Abstraction and Advanced Modeling
IC Compiler supports multiple design styles from full-chip flat designs to complex hierarchical designs. The modeling technology within IC Compiler supports mixed levels of abstraction. Concurrent Hierarchical Design allows designers to proceed with feasibility and implementation using blocks that are at varying states of completeness. For example, physical black boxes that represent RTL modules yet to be synthesized or custom macros yet to be created can be used in a top-level design along with standard cells, soft macros, and hard macros. The designer is able to use the model that corresponds to the most accurate abstraction level available for each block and proceed with top-level full-chip timing analysis and implementation.
For completed blocks, IC Compiler’s advanced ILMs now support multi-voltage and multi-corner multi-mode (MCMM) modeling while taking into account signal integrity effects. Placement optimization, clock tree optimization based on visibility into the model, top-level skew balancing, and route optimization are all available when using ILMs for top-level design optimization and closure, ensuring fast and accurate top-level runs.
Low Power Design
IC Compiler’s Concurrent Hierarchical Design supports low power techniques and multi-voltage designs. The placement engine recognizes voltage domains and keeps cells of voltage domains close together. This natural placement drives automatic shaping and positioning of voltage areas. Once voltage areas are defined, automated IR-drop driven PNS creates power meshes for all voltage areas simultaneously. PNS is extremely flexible and gives designers the option to specify requirements for layers, pitches, and rings of each voltage area. PNS first presents analysis data, such as IR-drop maps for each area, and if the power meshes meet desired specifications, then the designer can commit the meshes to actual, physical power routing.
Figure 3. Multi-voltage aware PNS and MTCMOS switch array optimization
In addition, IC Compiler has a number of capabilities that support the creation and use of MTCMOS switched voltage areas (Figure 3). An explore command, specifically designed for MTCMOS switched voltage areas, helps designers quickly find the optimum switch array for the voltage area. As a design’s netlist is updated, actual current needs of a switching area may change. IC Compiler’s optimize function goes through an existing voltage area’s switch array network and automatically updates the MTCMOS power switches to meet the new current requirements – increasing switch sizes where more current is needed and reducing switch sizes where possible, thus providing more area for use in routing.
Explore Mode: Fast Automated Initial Floorplanning
The Explore Mode is a capability within IC Compiler that allows designers to auto-generate initial floorplans extremely fast. Once a set of varying placement constraints is specified, a complete floorplan is produced within a few hours. The Explore Mode makes it possible to quickly generate numerous different floorplans in order to explore the design space and rapidly arrive at the best starting point for the design. Floorplans are automatically assessed and ranked using different criteria such as routability, timing, DRC, and power. Explore Mode is available for hierarchical as well as flat designs.
MinChip Ensures Smallest Routable Die
Frequently, during the final phase of the chip design, the designer may be tasked with shrinking the die size so that the greatest number of die can be produced per wafer, thus lowering production costs. This manual process inevitably adds days or sometimes weeks to the design schedule.
IC Compiler’s MinChip technology automates this process and provides a predictable way to achieve the smallest routable die size. MinChip is fast, runs in a single pass, and is multi-voltage aware. Designers have complete flexibility when it comes to MinChip and are able to direct it to preserve or not preserve the relative placement of hard macros and if appropriate the design’s aspect ratio. Alternatively, MinChip can shrink the design in one dimension – height or width only.
Table 1 shows MinChip results for a number of customer designs. There are significant benefits from even relatively modest die size reductions; for example, shrinking a 6.8mm2 die by just two percent will yield an extra 80 die from a 200mm wafer.
Table 1. MinChip results for customer designs
|Design||Design Type(chip/block)||Design Statistics(instances/macros)||%Reduction|
|A||Rectilinear block,10 sided||540K/17||6%|
|C||Full chip,single ring peripheral IO||131K/31||7%|
|D||Full chip,single ring peripheral IO||275K/31||5%|
|E||Rectilinear block,8 sided||30K/0||11|
|F||Full chip,single ring peripheral IO||300K/50||5%|
MinChip can be applied to full-chips or individual blocks. For hierarchical designs, MinChip is used to determine minimum block sizes. Whatever the application, MinChip automates the process of finding the smallest routable design size. Designers aren’t required to develop costly manual trial and error flows. MinChip makes minimizing die size for first pass tape-outs practical.
IC Compiler is a complete flat and hierarchical physical implementation system with everything necessary to implement next-generation designs. It has a unified, Tcl-based architecture that includes a common GUI and leverages a single timer and common engines throughout each design stage. It enables powerful design planning and chip-level analysis features to handle large, complex designs and provides early analysis and feasibility exploration while delivering the smallest die size. With the addition of Concurrent Hierarchical Design, IC Compiler now seamlessly blends design planning and implementation with common engines that are physical hierarchy aware enabling a natural and intuitive way for designers to achieve the highest design predictability, productivity, and quality of results.
Mark Bollar is a Senior Product Marketing Manager focusing on design planning and routing technology in IC Compiler. He has been involved in the wireless communication, semiconductor, and EDA industries for over 20 years, holding senior-level positions in both engineering, sales, and marketing.
©2008 Synopsys, Design Compiler, Galaxy, Milkyway, PrimeTime and Star-RCXT are registered trademarks or trademarks of Synopsys, Inc. Any other trademarks or registered trademarks mentioned in this article are the intellectual property of their respective owners.