| Industry Insight|
Your Chip in Half the Time?
Recent research by Synopsys shows that design teams face new challenges to achieve better time-to-results for their complex chip projects. Synopsys technical solutions architect, Irwan Sie, and senior director of marketing, Rajiv Maheshwary, outline the key elements of a productivity solution.
Research suggests that only one third of chip design projects ship on time. Increasingly complex product requirements will only worsen the schedule pressure and make the design problem harder; design teams must overcome new challenges with each new technology node. Serious concerns are rising throughout executive management and design teams alike, on how to address the factors that can slip the project schedule.
Figure 1. Major Factors Affecting Project Schedule
The design community badly needs a remedy for better productivity – not simply at the task level, but across the whole chip design process. Now, more than ever, commercial success is a function of the design team's ability to meet the (ever-shrinking) chip schedule. Our long-term research commitment to investigate and develop productivity solutions mirrors this trend.
Three Ways to Improve Productivity
Our analysis has identified three key themes that can help design teams to improve productivity. Based partly on our research into the pain points that hurt designers most, these can mitigate project risk and accelerate time-to-results.
According to our research (Figure 1), software and verification impact chip schedules more than any other task. It takes a significant amount of project time to create test plans, achieve the required coverage and perform mixed signal simulation and system validation. Once the chip is available, it often is the software associated with the chip which becomes the gating factor for a chip design to reach volume production.
Unpredictability is the scourge of the design community. If you cannot predict with certainty how long a particular task will take, it is very difficult to guarantee the project schedule.
The difficulty of achieving design closure is one particular problem, but it isn't the only one. Many chip methodologies struggle to accommodate late specification changes. And managing increasingly complex sets of timing constraints can also delay tapeout by weeks.
So what's the antidote to poor time-to-results? Figure 2 is a simplified framework illustrating Synopsys' focus on key productivity aspects of the chip development flow, highlighting three ways to improve productivity. Our research suggests that using a software-to-silicon verification flow, using a convergent design platform and having access to a broad range of proven IP are critical to achieving better productivity.
Figure 2. Synopsys Productivity Focal Points
#1 Comprehensive Software-to-Silicon Verification Solution
The verification process becomes more efficient if it incorporates system-level, functional and mixed-signal verification within a single environment. An integrated solution has to span software and hardware domains and enables both earlier start and increased productivity of software development by providing virtual platforms and FPGA prototypes for pre-silicon software development. Having access to a comprehensive, integrated solution means that a verification engineer can work at a high level of abstraction to achieve fast runtimes, and still perform detailed analysis of custom circuitry where appropriate. A comprehensive verification solution will include:
Traditionally, algorithm designers have used standalone tools or programming environments to create and verify their system-level designs. Refining those designs towards implementation using this approach can be time-consuming and error-prone. In contrast, using a model-based electronic system-level (ESL) design creation, simulation and analysis environment that is tightly integrated with the entire verification platform, improves overall design and verification efficiency.
Functional verification productivity can be enhanced in several ways. An environment that supports a design-for-verification (DFV) methodology enables design engineers to specify design intent at the outset. Using assertions ensures that designs are verification-ready, and allows early and systematic detection of bugs. New verification technologies such as intelligent constraint solvers help designers to reach coverage goals faster by automating key tasks. The use of testbench automation tools, verification IP and code-checking technology all contribute to faster, better verification.
Low-power verification benefits from technologies that provide comprehensive verification of voltage-control techniques, which increase accuracy and accelerate time-to-market. Multi-voltage simulation allows verification of the functional states of a design in all different power modes, as well as accurate verification of power transitions and sequences.
Achieving tight integration of mixed-signal capabilities within the RTL verification flow means providing a unified verification environment that incorporates fast simulation speeds with high accuracy, excellent ease-of-use and advanced debugging features.
Functional Equivalence Checking
Quickly verifying RTL-to-netlist functional equivalence for ultra-large ASIC, SoC and FPGA designs has traditionally been a challenge. Complex designs use numerous optimizations and are composed of extensive datapath, memory and full-custom blocks. Functional verification tools with easy-to-use, full-chip coverage are a requirement for market leading design flows.
Virtual and Hardware Prototyping for Software Development and System Verification
The software component of many projects is increasing in size and complexity, and the progress of many of today's chip projects is held up by software development. There are, however, some ways to counter this.
A growing number of design teams recognize the boost to productivity from beginning software development before the hardware is available. The use of a virtual platform enables pre-RTL software development to take place and can help to remove the software bottleneck from the project schedule. Synopsys provides a fully integrated tool environment for developing, running and debugging virtual platforms, which comes with native SystemC TLM-2.0 support.
FPGA-based prototypes help designers improve their time-to-market and avoid costly device respins by helping them to find the last few hard-to-find hardware bugs, starting software development earlier in the design cycle and integrating hardware and software well ahead of chip fabrication.
Multi-core Verification Technology
Faster runtimes come from improvements in both software and hardware, and multi-core hardware platforms now offer an excellent opportunity to enhance tool runtime – assuming that the software is capable of exploiting the multi-core hardware. By ensuring its key applications are multi-core ready, Synopsys has improved the runtimes of many of its verification products. For example a 2X speed-up for circuit simulation using quad-core vs single-core platforms.
The VMM methodology defines industry best practices for creating robust, reusable and scalable verification environments using SystemVerilog. It enables verification novices and experts alike to develop powerful transaction-level, constrained-random verification environments. A comprehensive set of guidelines, recommendations and rules help engineers avoid common mistakes while creating interoperable verification components. The VMM Standard Library provides the foundation base classes for building advanced testbenches, while VMM Applications provide higher-level functions for improved productivity.
Feedback from a leading super-computer customer demonstrates a 2X improvement in overall verification productivity thanks to the use of Synopsys VCS® with native testbench (NTB) technology and adoption of the VMM.
Discovery AMS has been adopted by more than 100 Synopsys customers for mixed-signal verification. Many customers report 3–10x higher verification throughput over using only transistor-level simulation.
The use of Synopsys' Innovator virtual platform helped wireless handset design teams begin its firmware, driver and OS development and porting six to nine months before silicon became available. FPGA prototyping using Synopsys' Confirma helped a Wimax 802.16e startup design team cut its overall project schedule by six months.
#2 Convergent Design Platform
Managing design implementation using a convergent platform means having excellent correlation between steps in the design flow, and advanced technologies and automation that work predictably to reach design closure quality so that your chip is ready for tapeout.
Design tools that share analysis engines and are tightly correlated can predict how different activities will affect the design – early prediction is vital for efficient design planning and feasibility analysis. Intelligent look-ahead technologies can predict and avoid downstream issues, which means less iterations are required to achieve design closure. Intelligent look-ahead design is especially beneficial where it enables synthesis to create a better starting point for the place and route process. Similarly, manufacturing-aware place and route creates a better starting point for design for manufacture (DFM) and sign-off.
Quality of results can also affect productivity. For example, improving routing quality by using fewer vias, less notches and jogs, makes for a smoother path to manufacturing.
Automated Digital and Custom Implementation Flow
Platform integration improves the automation of tasks, and makes it possible to perform advanced design functions such as multi-corner, multi-mode (MCMM) analysis. Concurrent MCMM throughout the flow accelerates closure for timing and power. If you can predict and fix congestion issues before place and route, you can speed-up each iteration.
Custom analog mixed signal (AMS) is a key ingredient in today’s consumer-driven SoC designs. In today’s designs we observe that custom and digital functions are highly interdependent, analog IP usage is mainstream, and embedded memory is on the rise. Legacy environments retrofitted to address today’s AMS design challenges are incomplete, inhibit interoperability, and are unproductive.
A new, intuitive environment that addresses both custom design and verification, natively built on OpenAccess to ease migration --uses open PDK libraries to promote interoperability, and unifies the process of digital and analog design -- will significantly enhance SoC designer productivity.
Reducing the die size is another example of a task which, if automated, improves time-to-results. With a growing focus on cost reduction, shrinking the chip area is becoming more important than ever and can take weeks of time when done manually.
Comprehensive Power Management
Advanced low-power techniques can dramatically reduce power and cost while increasing the performance and functionality of chips. The UPF standard allows easy and accurate capture of low-power design requirements. Specifying low-power requirements at the start of the chip design process allows the implementation of advanced low-power design techniques to be automated. These include automatic hierarchical clock gating, top-down multi-voltage synthesis and design planning, multi-threshold leakage optimization, low-power placement, power-aware clock tree synthesis, power gating, state retention, power network synthesis and analysis, and automatic test pattern generation.
DFT insertion tools add scan chains into designs to assist automatic test pattern generation (ATPG) tools in achieving high defect coverage. The most advanced ATPG solutions also have diagnostics capabilities that accurately pin-point the source of test failures and feed this data directly to yield management solutions to enable faster yield ramp-up. At smaller geometries, on-chip process variations can add enough extra delay to adversely impact circuit timing so that parts no longer function within specifications. Consequently modern ATPG tools need to create a variety of deep sub-micron (DSM) tests to maintain high defect coverage. The most advanced ATPG solutions now include power-aware pattern generation to reduce switching activity during test.
Scan compression tools synthesize on-chip compression logic to significantly reduce both test application time and test data volume. The most advanced tools work with implementation flows to achieve high compression with minimal impact on die size, routing congestion and circuit timing.
Hierarchical Design Automation
Designers have long used hierarchy as a way of managing design complexity. A design environment that enables concurrent hierarchical design can improve tool runtime and capacity, and allow you to more easily make changes to sub-blocks in the design hierarchy. A hierarchical design approach can also be more amenable to the use of multi-core processing, which also allows you to manage larger, more complex chips more efficiently.
Multi-core Implementation Technology
Running on quad-core platforms, key Synopsys implementation and sign-off tools show a 2-3x run-time improvement over single-core platform.
Out of the box methodologies, provided with design environments in the form of scripts that run the tools, enable designers to become quickly productive. As well as making the tools easier to use, they allow new technologies and techniques to be readily adopted. Typically, methodologies will be adapted for each major part of the design flow such as synthesis, design planning, place and route and sign-off.
After switching to Synopsys’ Galaxy™ Design Platform, a wireless design team reduced RTL-to-GDSII time to results from 14 days to two days for an ARM1176 processor core running at more than 600MHz using 45nm process technology.
Moving from a flat to a concurrent hierarchical design methodology enabled a mobile multimedia processor team to reduce total design turn-around-time by 40 percent on a six million gate, 90nm chip.
Leading technologies in the Galaxy Design Platform helped a consumer SOC design team to achieve smaller die area and meet reduced power targets on a complex 250 million transistor 45nm device.
#3 Access to Quality IP
According to Synopsys’ most recent survey, two-thirds of all designs now undergo at least one re-spin, and almost half of all re-spins are caused by functional problems within IP blocks.
There are three clear benefits of having access to a broad portfolio of pre-qualified commercial IP. We have seen that it is possible to reduce the IP qualification schedule by 30 percent and the cost by 20 percent, and we can also considerably reduce the risk of having to re-spin the silicon.
Synopsys provides a broad portfolio of IP for interfaces, bus fabric and memories, as well as traditional library elements, complex IP cores and verification IP.
According to the design team that delivered the world’s first dual HDTV decoder chip, using Synopsys’ DesignWare® and an IP-based assembly flow proved 2.5x more productive than the approach they had used previously. Any team looking to achieve optimal productivity improvements will find it necessary to use good quality IP, including models that support both design and verification.
While adopting any of these productivity solutions can reduce design time, the most efficient approach is to put a comprehensive strategy in place that will intelligently use of all of them. This puts you in the best possible position to substantially reduce chip design schedule as indicated in Figure 3 and enable you to capture new market opportunities.
Figure 3. Example Time-to-Market Gain on Consumer SoC
About the Authors
Irwan Sie is a technical solutions architect at Synopsys and has over 19 years of design engineering experience. Prior to Synopsys, he was director of IC Design at ESS Technology working on many successful digital video and audio multimedia SOCs, and has held senior engineering positions at VideoCore Technology, Philips Semiconductors, and Sun Microsystems where he worked on the design and verification of SuperSPARC® microprocessors and was awarded the Sun Microsystems Engineering Excellence Award. He holds a B.S.E.E. from Rutgers College of Engineering and M.S.E.E. from Lehigh University.
Rajiv Maheshwary is senior director of solutions marketing at Synopsys, responsible for customer marketing and time-to-results strategic initiatives. Mr. Maheshwary has over 20 years of IC design and EDA product and strategic marketing experience, holds a B.S.E.E. from Worcester Polytechnic Institute, an MBA in marketing from Lucas Graduate School of Business at San Jose State University, and a Japanese Language Business Proficiency Certificate from Berlitz and the Japan Foundation.
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