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SNUG Europe 2007
Wednesday 10 and Thursday 11 October
Kempinski Hotel Airport Munich


SNUG Europe has moved from May to October in the EDA event calendar. Other than a change of date, the event will follow the same successful format of previous European user group meetings. Read on for the essential event information, and to find out what sort of designers you might meet there.

The agenda for the 16th Annual SNUG Europe builds on the strength of previous years’ events offering a high-quality technical program focused on the specific needs and interests of European designers. Prior to the event, the user-driven technical committee reviews all of the submitted content to ensure that this is the case.

Synopsys' Chairman of the Board and CEO Aart de Geus will open the conference with the keynote speech before the technical program begins.

The technical program will focus on key design challenges, including front- and back-end implementation, low power design and verification, signoff, analog mixed-signal. In addition to the programs on chip design there will be an emphasis on multi-technology systems. This addresses designers working within industries such as automotive and aerospace facing increasingly difficult challenges in optimizing mechanical and electrical systems to work together. Two tracks will be dedicated to user presentations and tutorials around the use of Synopsys’ Saber multi-technology system simulation product.

Synopsys user group meetings provide a global forum that allows designers to learn from one another. There will be many opportunities to talk informally with fellow users as well as Synopsys product experts and executives, including a Wednesday evening reception.

Snapshot Profile
Exactly who from the design community are you likely to meet at SNUG Europe? Last year's event attracted over 360 users representing 90 different companies. There were 45 presentations from users among the total of 70 contributions from all authors, presenters and panelists.

Based on survey data from 2006, our snapshot profile of the typical SNUG Europe attendee reveals that your fellow attendee is most likely a design engineer. ASIC vendors are also well represented at the European conference. Like his global colleagues, your fellow attendee is almost certainly working on standard cell-based SoC design.

For a region that has traditionally specialized in low-power design and mobile communications, it’s perhaps surprising to know that over a quarter of attendees in 2006 were working on designs with clock speeds of 500MHz or above. Interestingly, the median clock speed is down from that reported in 2005, perhaps reflecting a trend towards the use of multicore architectures to achieve higher performance at lower clock frequencies.

More than 50 percent of design activity is focused on processes of 90nm or below and adoption of 65nm technologies is strong.

Communications is the most popular chip design category for Synopsys users on a global basis. This is also the case in Europe.


Profile
SNUG Europe Attendee Design engineer
Company ASIC vendor, IDM, System house
Process technology 90nm, moving to 65nm, standard cell SoC
Application Wireless, automotive, consumer
Frequency Spread – low speed design to very high speed
Methodology ASIC and COT
Verification strategy Strong trend towards SystemVerilog based testbench and assertions
IP experience Standard interfaces, Microprocessors, on-chip interconnect
Table 1. Summary Profile of the Typical SNUG Europe Attendee

Design Flow Choices
The customer-owned tooling (COT) design flow is very popular in Europe. This is also true globally: the majority of designers prefer a COT route, although ASIC vendors are getting increasingly involved in European chip projects again after several years of steady decline.

Functional (logic) problems are the main reason for chip re-spins in Europe. However, the vast majority of projects are limited to a single re-spin or none at all – figures that are significantly below the global averages for chip re-designs.

According to feedback from SNUG attendees in 2006, the adoption of SystemVerilog Assertions is expected to increase substantially as users move away from other assertion languages and begin to use more advanced verification techniques.

Intellectual Property Trends
The global profile shows an increasing preference to deploy third-party IP within a design: the average number of IP blocks is on the rise in all regions. European designers follow the global trend of having USB at the top of their IP shopping list.

While this snapshot of a SNUG Europe designer provides a profile of a typical attendee, it does not capture the diversity of interests and expertise of the group as a whole. Whatever your technology specialization, SNUG Europe is a forum where you will find people with an overriding common interest: sharing information and best practices to find creative solutions to common design challenges.

The Synopsys team looks forward to welcoming you.

SNUG Europe 2007
Wednesday 10 and Thursday 11 October
Kempinski Hotel Airport Munich

Technical Chair: Frank Poppen, OFFIS Research Institute

Find program details and register at:
http://www.snug-universal.org/europe/europe.htm

For more information about SNUG Worldwide, including information on your local SNUG event: http://www.snug-universal.org


©2010 Synopsys, Inc. Synopsys and the Synopsys logo are registered trademarks of Synopsys, Inc. All other company and product names mentioned herein may be trademarks or registered trademarks of their respective owners and should be treated as such.


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