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Power Planning Billion Transistor FPGAs with Astro-Rail
With Altera’s latest Field Programmable Gate Array (FPGA) designs exceeding a billion transistors, fast analysis without compromising accuracy is needed to optimize the power rail network. Yaron Kretchmer from Altera, and Li-Pen Yuan and Shekhar Kapoor from Synopsys, outline a novel approach based on the use of Synopsys’ power rail analysis tool, Astro-Rail.
Altera sees power grid planning as a critical step in the design process, especially for their latest custom designs targeting 65-nanometer (nm) processes. The power grid must be designed to accommodate the voltage drop that occurs through the package pins, bond wires and pads, as well as along the metal layers on the die itself. With power rail planning, Altera’s aim is to ensure that the power requirements are met across the entire FPGA.
Without it, the operating performance of the FPGA will be reduced, the design will be less immune to noise, and there is potential for functional failure. What’s more, because supply voltages are reduced in line with process geometries, the voltage margins available to accommodate voltage drop are decreasing, which makes accurate analysis more important than ever.
Electromigration (EM) is another issue that becomes more pressing as feature sizes decrease. EM is caused by high current densities creating metal migration, resulting in open or short circuits. EM also causes performance and reliability degradation over time. It can be minimized by paying attention to power grid planning.
For ASIC designs, voltage analysis tools are proven on production designs. Altera teams faced the problem of analyzing full-custom, billion transistor FPGAs with a die size in excess of 20mm on a side. Such a design posed a new set of problems that challenged the way power rail analysis was performed.
Custom FPGA Design Parameters
Altera’s full-custom FPGA designs consist of a number of carefully crafted block types replicated multiple times. The blocks are connected by abutment. This design style leads to a complex power network, with around 600 power pins per block, although some blocks use in excess of 6000. Clearly this level of complexity places demands on analysis tools that are far beyond most ASIC design projects.
A key aim for Altera teams is to achieve a reasonable turnaround time for power grid analysis using fairly standard high-end computers. With 64-bit machines supporting 60GB of memory, the objective is to complete an analysis in 24 hours and analyze incremental changes even faster. Accuracy is also an important requirement. Altera teams demand analysis results within 10 percent of actual silicon measurements.
As the Altera designers develop full-custom cell designs, they must also manually create the models required to support voltage drop analysis. In order to ensure the power analysis flow is easy to adopt, the models should provide a simple way of modeling complex behavior. This is key to allowing efficient analysis to take place.
Model Support within Astro-Rail
Altera’s standard power network analysis tool is Synopsys’ Astro-Rail, which supports ASIC as well as full-custom designs. Astro-Rail offers a choice of modeling techniques.
White box models are preferred for sign-off purposes because the entire connectivity of the power network can be modeled in a block, and voltage drop results are provided on every node inside the block. However, the size of the network is directly proportional to the complexity of the block’s power network. Theoretically, white box models provide more accuracy but at the expense of memory. For example, a full-chip model of a one billion transistor design requires around 300GB of computer memory.
Gray box models use the resistance between ports of a block to support the analysis, and results are provided only on those ports. The size of the model is determined by the number of ports of the block – it scales quadratically with the number of ports.
The challenge is to find a modeling approach that satisfies the requirements in terms of memory size, accuracy and runtime performance, given the huge number of instances and ports that are present in large, complex custom designs.
Gray Box Pin Reduction Modeling for FPGAs
Measuring voltage drop by probing real FPGAs confirms that most of the voltage drop occurs in the topmost metal layers. The majority of pins, however, exist at the lower layers. By understanding the physical properties of the design, it is possible to adopt an approach that keeps the upper layers intact while removing the lower layer pins from the model. Theoretically this should result in a dramatic reduction in the model size, while maintaining the accuracy of the voltage drop measurements.
Figure 1. Pin Reduction at Lower Levels
The Altera Approach
The approach taken by Altera preserves the top five layers and successively removes pins from the lower layers. The team used a test case block to enable the pin removal approach to be validated. The designers eliminated only those pins closer than a specified distance, and they correlated the results against the white box model. By doing this, they could see how far this technique could be taken before the voltage drop error became unacceptable. They found that while reducing up to 75 percent of the lower layer pins has little impact on the voltage drop error, the technique is of major benefit in reducing the memory demands by almost 6x for the gray box model.
With the test design, memory consumption decreased from an estimated 300GB to around 16GB. Scaling these results to the 1B transistor full-chip design gave a memory consumption requirement of 56GB – within the 60GB target supported by the 64-bit machine.
Full-Chip Analysis: 3-Step Process
Support for pin reduction in Astro-Rail ensures that voltage drop analysis is feasible across the full chip. Because gray box modeling returns voltage drop values for the pins at the periphery of each block, it can be used for initial block-level analysis. A further requirement is to understand the worst-case voltage drop within the blocks.
Once the most vulnerable blocks are identified, it is possible to push down from the top-level results to perform an in-context block-level analysis. The voltage drop values for the pins serve as boundary conditions to enable accurate instance-level analysis. The key steps are summarized below and in Figure 2.
Figure 2. The Complete Voltage Analysis Flow
Step 1. Block-Level Analysis
Extract pins from the block GDS, and reduce the number of lower-layer pins to enable efficient use of memory. Save the resulting gray-box models in a block library for use during top-level analysis. SPICE simulations can be used to derive the power consumption for each cell, or the cell-level power budget is specified by the designer. It is beneficial if the power budget can be allocated within a cell in different ways. Intra-cell power budgets can for example, be based on measurements from previous devices. Separate analysis runs for VCC and VSS rails provide a combined rail degradation figure.
Step 2. Top-Level Analysis
This process provides the location of the blocks from the full-chip GDS. The top-level analysis reveals the voltage drop and EM values for each pin. Typically the placement information will be extracted using a physical verification tool.
Step 3. In-Context Block Level Analysis
Use the voltage drop/EM values obtained in Step 2 as boundary conditions for an in-context cell level analysis. This enables derivation of the exact worst-case location. For an in-context analysis, the complete description of the cell is needed, and not just the pins, which is why the original cell GDS is used.
Correlation with measurements from silicon samples provides validation of the analysis results. However, measuring on-silicon drops must take into account the package effects, and also that voltage drop analysis performs static current consumption while the real silicon will also consume power dynamically.
To enable a true comparison with the results of the static current analysis, the test FPGA device was programmed to consume static current only. By measuring the voltage at multiple points across the die, the voltage drop was accurately calculated.
By taking measurements from the silicon die itself, any error due to voltage drop through the package could be eliminated. Special vias were built in to the test chip to enable measurements to be taken from the lowest metal layer (M1).
Test Chip Analysis Results
The worst case results from Astro-Rail were 11 percent lower than the measured results obtained by probing the test chip. Temperature variations can increase metal sheet resistance by between 2.5 – 8 percent typically, and this is not accounted for in the analysis models. Compensating the models for resistivity changes due to temperature variation brings the analysis results to within 5 percent of the measured silicon voltage drop – within Altera’s 10 percent target.
The application of gray box modeling combined with pin reduction techniques dramatically reduces the memory requirements for performing power rail analysis with Astro-Rail, without compromising accuracy. Performing accurate analysis on full-custom designs of a billion transistors or more presents new challenges in managing both capacity and runtime.
This new approach, which combines ease of use with performance and accuracy, is enabling Altera’s design teams with the ability to improve both productivity and predictability in the quest to tackle one billion transistor designs – and beyond.
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