| Technology Update|
Sign-Off: Statistical Revolution Needs an Evolutionary Approach
Sign-off is a hot topic, as designers get to grips with the increasing uncertainty due to the variation characteristics of advanced processes, and an increasingly complex relationship between implementation and sign-off tools. The EDA industry is awash with talk of “correlation”; just as a major shift towards statistical techniques is also taking place. Robert Hoogenstryd, Director of Marketing, Design Analysis and Sign-off, looks at what correlation really means, and advocates an evolutionary approach to the introduction of variation-aware sign-off.
Like many things in life, it's easy to look back at the 'good old days' of semiconductor design with affection. At the moment this is particularly true in the field of sign-off, which – if some observers are to be believed – is currently undergoing a revolutionary upheaval.
Traditional ASIC Sign-Off
In the days of the traditional ASIC design flow and business model, the sign-off stage was a well-defined – and key – point in the process of making a chip. The designers would complete their front-end design and gate-level implementation, run timing sign-off using a static timing analysis tool such as Synopsys PrimeTime®, and hand the design to the ASIC foundry along with the timing constraints. The ASIC foundry would complete the back-end design to those constraints and provide timing information back to the design team, which in its turn would re-run their PrimeTime analysis to verify that – as far as it was possible to be sure, the chip would work at the required performance.
All being well, that was the point at which the design and manufacturing teams would meet and agree to 'sign-off' the design. In essence, the customer would bring to the table a set of design performance criteria, and a netlist known to meet those criteria; the ASIC foundry would have verified that those criteria would be met by the chip they intended to manufacture. Therefore the design was good and if there were to be any future issues with respect to silicon failure, responsibilities were clearly defined.
COT Changes Sign-Off Process
In these days of the fabless model and customer-owned tooling (COT), however, the meaning of timing sign-off has changed dramatically. The foundry will certify their SPICE models, DRC and LVS runsets, extraction models and IP libraries, but provide few solid guarantees beyond that point. As the industry has become dis-integrated, the design team has had to take responsibility for physical design closure with adoption of a COT-based flow - hence timing sign-off has moved to an internal customer criterion of readiness verses a formal handoff criterion to the foundry.
But that does not mean that the importance of sign-off has diminished: far from it. If anything, sign-off tools are more critical than ever. Ahead of any other part of the flow, the design team needs to trust its sign-off process to pinpoint problems prior to manufacturing: only in this way can they reduce risk to an acceptable level, ensure design integrity, and keep design costs in check.
As a result, sign-off tools have evolved in two very important ways over the last several years. First, a tool like Synopsys PrimeTime now provides much more than just an accurate timing engine via static analysis and delay calculations. For example, today's PrimeTime Suite includes PrimeTime SI, a signal-integrity solution that provides advanced delay calculation with crosstalk and noise effects; and PrimeTime PX for integrated gate-level power analysis. Tight links to other Synopsys tools such as Star-RCXT for parasitic extraction, and NanoTime for transistor-level modeling, are also important.
Figure 1. PrimeTime® Product Suite
The second evolutionary consequence is the need for tighter links between design implementation and sign-off. With the customer assuming responsibility for design closure in a COT flow, it is critical that the path between implementation and sign-off is predictable. Poor correlation between design and sign-off increases the risk of costly and time-consuming iterations back to place and route. Adding new sign-off criteria, such as power and signal integrity, substantially increases this risk if the design tools cannot accurately predict sign-off.
But as the industry has adjusted to these long-recognized developments, another, potentially more disruptive factor has reared its head: increased process variation. At 65 and 45nm, the effects of inter-die and intra-die variations become significant: timing, parasitic extraction, signal integrity and a host of other factors need to be dealt with by variation-aware techniques.
The revolutionary nature of this change in thinking has led many in the industry to speculate that the time is right for a corresponding revolutionary change in sign-off tools. The move to statistical techniques, they maintain, requires wholesale re-tooling; and increased integration means that it makes sense to use a unified timing engine throughout the implementation flow, to improve correlation between tools.
But at Synopsys, the conclusion is that quite the reverse is true. With re-spins more costly than ever, and responsibility now firmly with the customer, it makes little sense to increase risk by throwing away trusted techniques and gold-standard tools. Sign-off is an area that requires a tremendous investment, not only from the EDA provider, but also from the design and verification teams who use the tools. A tool like PrimeTime becomes trusted by virtue not just of the time and person-resources needed to build the tool itself, and its resultant performance and capacity. Such a tool also needs to be honed in-use by the experiences and contributions of a wide range of customers, undergo rigorous vendor and foundry qualification with a variety of types of design over a long period of time. And every design team will need to invest substantial time and effort to tune its sign-off methodology to their particular flow and design style. Synopsys has paid much attention to all of these areas over a long period of time in order to build a market-leading position in sign-off tools and technology.
Introducing New Technology
Synopsys has maintained an evolutionary approach to developing the sign-off offering, seeking to preserve the trusted nature of the tools and yet still introducing new technology where it is required. This method is exemplified by the progressive introduction of statistical timing analysis and other variation-aware techniques, with seamless integration into PrimeTime, rather than starting from scratch and re-tooling.
Figure 2. Introducing Variation-aware Analysis
In this case, evolution works on several levels, not least because in many cases design teams are still struggling to come to terms not only with the detail of variation-aware design, but also with the higher-level questions of whether – and when – they need to know about it. Synopsys' approach is to allow customers to adopt at their own pace, retaining a foundation that they trust, rather than expecting them to make a sudden jump. Thus the introduction of variation-aware analysis by integrating statistical technology within PrimeTime STA and Star-RCXT parasitic extraction, delivering enhanced analysis capabilities with the benefits of tried, trusted and accurate tools.
At the same time, advances in modeling technology have brought a move to open, unified composite current source models within the Liberty library format. As a result Synopsys provides comprehensive, accurate and efficient modeling of nanometer effects and enable designers to perform complete timing, noise, and power sign-off using a single, open library model.
It is also worth remembering that statistical timing analysis, while a promising emerging technology to model variation effects more accurately, in itself is not a panacea. Functional modes, environmental temperature and voltage range, temporal thermal effects, IR-drop, SI are all conditions that must be modeled in sign-off but cannot be represented or are difficult to represent statistically. So corners, bounded techniques, margining, cross-talk analysis, multi-scenario and statistical analysis must all work together in concert to provide a complete solution.
In addition, statistically-enabled timing sign-off tools need to meet all the requirements of STA sign-off tools: accurate delay calculation, accurate delay propagation, correct handling of topological correlation (convergence/re-convergence), correct handling and interpretation of design constraints, reporting, what-if-analysis, debugging features, ECO flow integration, and so on.
Given these fundamental requirements, Synopsys' aim is to build on the tools that designers already trust in this area, whilst still handling all of the sign-off requirements and simultaneously introducing the additional margin reduction capabilities that are required at 65nm and 45nm: capabilities that today already come as an integral part of the PrimeTime/Star-RCXT foundation.
Implementation and Correlation
Synopsys has taken the same approach with the issue of correlation, an area of active development for the company over the last several years. Whilst top-down integration into the implementation flow looks attractive on paper, in fact sign-off tools need to be designed with attention focused downstream, toward manufacturing: the inviolable need for correlation is with HSPICE and the silicon itself. To achieve this requires uncompromised accuracy from the sign-off tool.
Implementation tools, in contrast, have to run as fast as possible to improve designer productivity, and will therefore inevitably need to trade some degree of accuracy for the sake of performance. The key is to optimize this trade-off and to test extensively to ensure a good correlation between place and route and sign-off tools. The importance of this cannot be overstated. One of the key strengths of Synopsys' sign-off technology is the consistently accurate correlation achieved based on a sign-off regression suite consisting of well over 3000 test cases.
This bottom-up approach extends to front-end correlation with the introduction topographical synthesis within Synopsys' Design Compiler® to better predict post-layout design performance from the point of view of timing, power and area.
So, while Synopsys recognizes that sign-off is one of the most challenging areas in the EDA flow as the industry moves to 45nm production, design teams are extremely wary of moving away from tried and trusted gold-standard sign-off tools. For many customers, timing sign-off may no longer exist as formal hand-off deliverable between themselves and their foundry, but it's more important than ever to silicon success. Designers must therefore embrace an evolutionary approach, in which statistical techniques and variation-aware technologies take their place beside some of the most robustly tested and well-trusted tools and techniques in the industry today.
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