| Technology Update|
Addressing Process Variation in 45nm Designs
At 45nm technologies and below, new sources of process variation must be tackled during the design process. Terry Ma and Xi-Wei Lin from the Synopsys TCAD group explain how process-aware design-for-manufacturing (PA-DFM) technology from Synopsys helps designers to understand and address the underlying physical issues.
The successful introduction of new semiconductor processes with smaller and smaller feature size depends increasingly on the use of advanced manufacturing techniques to enhance performance of the structures implemented in silicon. One of the consequences of adding new manufacturing techniques to enhance performance is a growth in variation in the characteristics of the process across the wafer and chip. Process variation is also made worse by higher levels of complexity in the design and the demand for higher performing chips. When optimizing the chip layout for manufacturing in 65nm technologies and beyond, designers have an additional responsibility: they must identify and account for manufacturing variability in the design.
New Sources of Process Variation
At 90nm geometries and above, designers learned to manage on-chip variation arising from voltage and temperature effects, which if ignored make it hard to achieve timing closure. With accurate modeling, issues such as IR drop, RC delay and signal integrity can be taken into account within the design process without excessive guardbanding or having to apply overly conservative design rules that leave performance on the table, or increase area or power.
But with the latest technology nodes, the use of new manufacturing techniques, such as strained silicon, introduce new sources of variability into the chip.
Strained silicon is a manufacturing technique that improves the performance of transistors fabricated in advanced technologies by increasing carrier mobility. Transistors switch faster and circuit performance is greatly enhanced. Consequently, from 65nm onward, strain engineering is intentionally used to improve the current drive by changing carrier mobility. However, the process of strain engineering also introduces stress proximity effects into the silicon that can create significant variation between transistors. Layout dependency may create delay variations of 10 percent or more, with the problem increasing as geometries scale to 45nm and below. Unlike lithography effects (e.g. optical proximity correction), there is a lack of accurate models to address the process variability introduced by strain engineering at the design stage.
Compared to earlier sources of on-chip variation, stress effects are non-intuitive and more difficult to comprehend. Several factors influence stress-induced mobility variations, including the layout context, stress sources, directional stress components and the type of MOSFET.
In addition to proximity variations arising from stress effects, it is also necessary to address global variations that occur due to the spread of manufacturing process parameters across different die and wafers. If proximity and global variability is not properly addressed, chip failures will result and parametric yield will suffer.
The key to dealing with process variation is accurate process and device modeling. However, the introduction of a process-aware capability into the design flow should neither burden the designer with complex information nor force the design team to make major changes to the physical design flow. Thus, the solution should be incremental and be easily plugged into the existing design flow.
Synopsys' PA-DFM product family is uniquely equipped to account for transistor variability, addressing the parametric variations that arise from design and manufacturing interactions by integrating accurate physical modeling information in the design process. With the introduction of the PA-DFM tools, Seismos and Paramos, custom designers have the ability to analyze and address process variability issues at the design stage without changing their existing design flow.
Figure 1. Synopsys Yield Analysis Tool Portfolio
The PA-DFM products are built on Synopsys' TCAD expertise in advanced process and device modeling, and allow custom designers to account for manufacturing variability without major changes to the standard physical design flow. Seismos and Paramos address both of the sources of variability identified earlier: proximity variation due to stress and other proximity effects, and global variations due to the spread of manufacturing process parameters across die and wafers.
PA-DFM links manufacturing variation information back to design, enabling custom designers to optimize their layout for yield optimization. This capability enables designers to realize the full potential of advanced semiconductor processes, while improving predictability which reduces the need for chip respins. Seismos and Paramos complement Synopsys' PrimeYield suite of yield-analysis tools, as well as PrimeTime® VX statistical timing analysis and Star-RCXT VX statistical extraction tools.
Seismos provides transistor-level analysis of stress and other proximity effects in nanometer strained silicon technologies. Seismos uses accurate models based on rigorous TCAD simulations validated by silicon data. It has the capacity and performance to deal with a broad range of design complexities, from a few transistors to multimillion-transistor custom designs. As well as performing stress and proximity analysis on the layout, Seismos annotates these effects back to a SPICE netlist, enabling assessment of their impact on the overall performance of the design. This assessment is facilitated by the provision of a graphical user interface to enable data visualization and real-time what-if analysis in the layout environment.
Making accurate manufacturing information accessible to the design process is key to enabling successful DFM. Paramos extracts process-aware SPICE models that combine calibrated TCAD simulations and global SPICE parameters to enable detailed analysis of circuits. This approach allows the simulation of circuit responses to specific process parameter variations such as implant dose, spike anneal temperature, gate critical dimension and gate oxidation temperature.
With Paramos, custom designers can develop a physically-based variation model for statistical timing simulations of circuit performance, allowing exploration of design sensitivity to real physical process parameters.
Design Flow Integration
Synopsys' PA-DFM tools fit into the custom back-annotation design flow and link to other Synopsys tools through GDSII, layout schematic and SPICE netlist.
Seismos takes in GDSII and the design netlist to start the analysis. The input netlist can be the ideal case generated directly by Hercules LVS, or one with RC parasitics generated by a combination of Hercules and Star-RCXT. In addition, Star-RCXT provides x-y coordinates of transistor gates for Seismos to analyze the effects of stress in circuit simulations. For 'what-if' analysis, the layout with Seismos stress and other proximity effects can be displayed through IC Workbench. The output of Seismos is a new netlist including device, RC, and stress-related parameters for simulation with HSPICE®, HSIM® or NanoSim®.
Figure 2: Integrating Seismos and Paramos in the Existing Custom Design Flow
In the case of Paramos, the input is the I-V and C-V data coming from TCAD (e.g. Sentaurus Process and Device) simulations. Paramos performs global extractions to generate process-aware SPICE parameters, which in turn will be used for HSPICE, HSIM or NanoSim simulation.
The Synopsys PA-DFM tools help to enhance design predictability by minimizing unknown process variations and providing variability analysis capability to reduce chip respins. Interactive 'what-if' analysis enables the design layout to be optimized without a time-consuming trial-and-error approach. By anticipating process variations at the design stage, designers can avoid conservative guard-bands and realize the full potential of technology scaling.
Seismos and Paramos are the core products in the PA-DFM product family. Synopsys will add new capabilities and products to address additional process variability issues arising from process scaling at 45nm and beyond.
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