Innovative Ideas for Predictable Success
      Volume 2, Issue 3

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Spotlight Why Power Standards Matter
Accellera recently approved the Unified Power Format (UPF) as the new standard for the industry’s low-power design flows. Gal Hasson, Director of Marketing for Synopsys’ synthesis and low power solution, explains why engineers care.

The debate on standards for low power has received a significant amount of news coverage of late. The focus of the coverage has too frequently centered on competing initiatives for a low-power standard. What is important and often overlooked are the real benefits that standardization delivers for the design community.

A New Accellera Standard
UPF 1.0 is the new Accellera standard for low-power design and verification, a single format that spans the entire low-power design flow. The standard is an extension of the HDL logic specification for describing power-aware design intent. It is based on a set of consistent semantics for implementation and verification, and enables power requirements to be captured at appropriate levels of abstraction while maintaining high accuracy.

The UPF standard is based on silicon-proven technology that has been donated to Accellera by a number of organizations with expertise in low-power design. Accellera has continued the standardization process by committing to transfer UPF to the newly-opened IEEE P1801 low-power working group.

Adoption Benefits
Low power has become a ubiquitous design goal over recent years – not just for battery operated and portable products, but for virtually every complex chip design. Until now there has been no industry standard to specify low-power requirements in a way that allows interoperability between power-aware EDA tools.

Adoption of the UPF standard will ensure industry-wide design portability for low-power projects. It is supported by multiple EDA vendors and guarantees the widest support for best-in-class tools throughout the design and verification flow. Because UPF makes use of Tcl side files, HDL code is preserved and so the standard can be adopted for legacy designs without the need to rewrite code.

UPF enables remote design teams to share low-power information more easily within the project and with third-party suppliers of IP and design services. Support for power-aware IP is another important benefit to design teams both designing and using commercial IP.

Use Model
The conceptual model for the use of UPF is to overlay power information on top of the design. This approach is supported at all levels of abstraction. Figure 1 shows the application of UPF data from RTL to GDSII.


Figure 1. UPF Supports Design and Verification from RTL to GDSII

As well as setting low-power requirements and constraints, UPF allows design teams to define the power distribution architecture including power domains, power islands and the related power network, as well as intended power-aware functional behavior (e.g. retention, isolation and shutdown).

This drives the implementation to create the required power architecture and allows verification tools to verify correctness of the power-aware characteristics of the design combined with the correctness of the design function.

Technology Donations
UPF is actively supported by the majority of EDA companies, and leading advocates of low-power design. Donors to the standard include:

  • Mentor
    • External power configuration file for verification
  • Magma
    • Power Management commands
  • Vast
    • System level modeling methodology and format
  • Synopsys
    • RTL constructs (Verilog and VHDL)
    • Power management commands
    • Switching activity format – SAIF
    • Power state table
  • TI
    • Retention cell semantics
  • Atrenta, Synchronous DA

Responding to Designer Demand
The Unified Power Format (UPF) is the industry standard for low power. This standard responds to the needs of end users, particularly manufacturers in the wireless communication sector who have consistently lobbied the industry to unite behind a common standard. Design teams, manufacturers, IP vendors and tool suppliers will benefit from the ability to easily share low-power design information, use more productive design flows and meet their product’s power budgets with greater success.

Synopsys fully supports this initiative, and has donated advanced formats and simulation semantics to Accellera. The company will continue to actively support the development of the standard. Today, Synopsys offers a silicon-proven power-aware end-to-end solution that is deployed by advanced design teams around the world. By enhancing the Synopsys low-power flow to be UPF compliant, designers will benefit from industry-wide interoperability of power-aware tools, IP and design skills that further improve design productivity in a low-power flow. The Synopsys low-power solution will add support for UPF during 2007.


©2010 Synopsys, Inc. Synopsys and the Synopsys logo are registered trademarks of Synopsys, Inc. All other company and product names mentioned herein may be trademarks or registered trademarks of their respective owners and should be treated as such.


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Author
Gal Hasson is Director of Marketing for Synopsys’ synthesis and low power solution.

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"Low power has become a ubiquitous design goal over recent years – not just for battery operated and portable products, but for virtually every complex chip design."