Innovative Ideas for Predictable Success
      Volume 2, Issue 2

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  Industry Insight
Spotlight Helping the Industry Meet New Challenges
Synopsys is at the heart of the electronics vortex, working with IC companies at every stage of chip development. From this viewpoint, Aart de Geus looks back on 20 years of success and discusses the forces that continue to shape the semiconductor industry and make EDA a compelling enabler.

It is an exciting time for the electronic design automation (EDA) market. Consumer demand is driving technology advances at an astounding rate. This is particularly noticeable in consumer electronics, where the industry has grown in the last 20 years from voice to data to video. Video, especially, is everywhere now and will continue to grow rapidly in a broad range of consumer products, driving the need for processing power, storage, bandwidth, software and displays. The demand for portable media players, digital cameras, video game consoles, flat-panel televisions and converged mobile devices dictates unprecedented performance requirements in chips.

To meet these requirements and stay competitive, chipmakers must be at the forefront of technological progress and use advanced EDA solutions to optimize chips for speed, power and battery life, while simultaneously achieving economic viability. Before looking at the challenges of the future, a review of the key changes in chip design will provide a perspective on just how far the industry has come.

Traditional Challenges
For the last 20 years, the semiconductor industry has achieved success by satisfying changing consumer needs. This has not been a simple evolution; going digital, for instance, has probably been the all-time single biggest contribution to human productivity in the last 100 years. The progress made in electronics has been truly astonishing ever since. At the heart of this progress is the capability to design and manufacture complex integrated circuits.

The degree of precision required in today’s designs is critical to the success of electronic devices. Customers want devices to be faster, smaller and lower power. They also want devices that work without fail. Since the 1960s, IC designers have risen to the challenge of meeting these demands. The greatest breakthrough has been the use of computers to simulate and automatically optimize designs, greatly reducing the time required to ensure that a chip will work exactly as specified before it is deemed ready for manufacture.

Today, the success of physical optimization is remarkable, especially considering that chips have grown substantially in complexity over the last 40 years, from designs with just one or two transistors to designs with over a billion. A successful chip requires that every single transistor in a billion-transistor design works and is connected without any mistakes. Advances in EDA have helped designers meet this challenge, but the tasks involved are once again becoming more difficult. Silicon structures are now so small that they are almost unpredictable.

A further challenge for chip designers is time; customers will not wait indefinitely for the newest electronic devices. Success in the electronics market depends on launching your product before the competition. EDA makes this possible at a viable cost for manufacturers of chips and end products alike.

For the last 20 years, Synopsys has invested in research and development to deliver successive generations of EDA tools that enable the design community to tape out advanced designs, while satisfying its time-to-market, performance, power, cost and functionality goals. Synopsys touches all the physical issues that need to be represented correctly on a chip to make it fully functional. However, while the design goals remain broadly constant, the way they are achieved is changing as new threats to predictable design continue to emerge.

Smaller Geometries Mandate DFM
In recent years the semiconductor industry’s priorities have shifted focus. It once viewed design and manufacture as independent disciplines and focused almost exclusively on achieving optimal size, speed and power. As long as a designer followed the rules, the design could be manufactured. Now, however, design and manufacture are becoming more and more intertwined and a failure to master this new interdependency will surely result in painful yield loss. Anything that can be done in design to improve yield has enormous value as it directly impacts the chip cost and thus the bottom line. This new priority is called design for manufacturing (DFM).

Before 65nm, yield loss was mostly due to random defects, but at today’s smaller technology nodes, the culprit is more often systemic defects. Successful DFM requires characterization of all the manufacturing steps and knowing how to change a design to compensate for negatives or to accentuate positives. For example, today it is possible to put stress in transistors to improve their conductivity. Because the stress is actually a function of neighboring transistors, the engineer must provide a sophisticated calculation to predict a transistor’s stress level and its electrical characteristics. Now that it is possible to make such calculations, Synopsys is looking ahead to the next step: modifying the design to put additional stress on those parts where a change in the transistor’s behavior is desired.

There is now a need to understand physics at 45nm – a scale far smaller than the 193nm wavelength of light used in photolithography! At today’s geometries, engineers use many complex lithographic techniques to improve the transistor’s resolution. Structures are so small that the variation in a parameter is often as great as the parameter itself. In stark contrast to the people at the other end of the spectrum who design the systems, there are material scientists who work with layers of just a few atoms, who, by tweaking one in every 25 atoms, can adjust the chip’s performance.

The Role of Synopsys
Synopsys’ role is to create design tools that understand phenomena that affect system functionality from the smallest scale to the biggest. Today’s industry challenge is to constantly devise and improve tools and technology to work at increasingly smaller technology nodes capable of managing – and anticipating – the new and sometimes contradictory rules that accompany evolving manufacturing processes.

In bringing its new tools to market, Synopsys aims to shield designers from complicated physics at a miniscule level. Design tools should take all the interacting physical problems and present the designer with a yield prediction. They should also summarize all the complex information that comes from manufacturing in a form that allows designers to make decisions and extract what’s most important at each layer, enabling designers of the next layer to easily take the next step in the design process.

The Future
Synopsys is in a strong position to provide DFM solutions and to continue to spearhead advances in implementation, verification and system-level development. Insulated from the traditional semiconductor manufacturing boom-bust cycles, the company can invest in the longer-term research and development critical to the advancement of modern design. With 20 years of innovation behind it, Synopsys will continue to drive EDA forward to sustain the industry’s unrelenting growth and meet the challenges of the next 20 years.


©2010 Synopsys, Inc. Synopsys and the Synopsys logo are registered trademarks of Synopsys, Inc. All other company and product names mentioned herein may be trademarks or registered trademarks of their respective owners and should be treated as such.


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About Aart de Geus
Chairman of the Board and Chief Executive Officer Since co-founding Synopsys in 1986, Dr. Aart de Geus has expanded Synopsys from a startup synthesis enterprise to a world leader in electronic design automation (EDA).

As a technology visionary, he is frequently asked to speak at electronics industry conferences, university graduate schools of business, and global conferences including the World Economic Forum and Fortune Brainstorm.

He was made a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) in January 1999, honored with the IEEE Circuits and Systems Society Industrial Pioneer Award for pioneering the commercial logic synthesis market. In 2002, he was named CEO of the Year by Electronic Business magazine, and in 2004 was named Entrepreneur of the Year in IT for Northern California by Ernst & Young. In November 2005, he was chosen by Electronic Business magazine as one of “The 10 Most Influential Executives.”

Dr. de Geus is a member of the board of the Silicon Valley Leadership Group (SVLG), TechNet, the Fabless Semiconductor Association (FSA), and is Chairman of the Electronic Design Automation Consortium (EDAC). In 1999 he created the Synopsys Outreach Foundation to promote project-based science and math learning throughout Silicon Valley.

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"Anything that can be done in design to improve yield has enormous value."