SoC Benchmark

Wide adoption of SystemVerilog to increase in 2007

Which testbench languages are used in your design? Currently
(N = 2083; Margin of error = +/- 2%); In 1 Year (N = 1269; Margin of error = +/- 3%)

Which assertion languages are used in your design? Currently
(N = 1140; Margin of error = +/- 3%); In 1 Year (N = 990; Margin of error = +/- 3%)

Which languages are used in your design project? Currently
(N = 2447; Margin of error = +/- 2%); In 1 Year (N = 1557; Margin of error = +/- 3%)

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