SoC Benchmark

Gate Count Trends
San Jose SNUG attendees demonstrate the trend towards larger designs over the 4 years between 2002 and 2006, with the greatest increase in design activity in the 5M gate plus category.

What is the gate count of your current IC design? (Assume 4 transistors = 1 gate. Include memory.) 2006 N = 479; Margin of error = +/- 5%

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