Chinese Edition of ‘A Practical Guide for SystemVerilog Assertions’
Synopsys has recently completed the translation into Chinese of an important technical publication for design and verification engineers: A Practical Guide for SystemVerilog Assertions.
Assertions are a key part of the SystemVerilog language. The use of SystemVerilog Assertions enables designers and verification engineers to encapsulate verification checks into the design. This enables a proactive approach for proving complex SoC designs.
Written by Synopsys verification experts and Applications Consultants, Srikanth Vijaraghavan and Meyyappan Ramanathan, the book explains the syntax and characteristics of the language in an easily digestable format, with the help of numerous code examples. The focus of this book is the use of the language to solve real verification problems.
"This book benefits both the beginner and the more advanced users of SystemVerilog Assertions (SVA). First by introducing the concept of Assertion Based Verification (ABV) in a simple to understand way, then by discussing the myriad of ideas in a broader scope that SVA can accommodate. The many real life examples, provided throughout the book, are especially useful."
Irwan Sie, Director, IC Design, ESS Technology, Inc.
The Chinese edition of the book has been translated by Synopsys Verification R&D manager Junjie Chen and Synopsys Senior Verification Engineers; Jinnan Huang, Carl Ye and Alex Yang.
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