Innovative Ideas for Predictable Success
      Volume 1, Issue 3

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  Customer Spotlight
Spotlight Moving to the Next Level in Verification Productivity and Predictability
Simon Lacroix, hardware developer, Ross Video, discusses how his team enhanced verification productivity and predictability, and greatly improved project timelines, by switching from a C environment to become first-time users of Synopsys’ VCS Native Testbench (NTB) and the Verification Methodology Manual (VMM) for SystemVerilog.

Video production equipment provider Ross Video successfully combined Synopsys’ VCS Native Testbench (NTB) and the Verification Methodology Manual (VMM) for SystemVerilog to dramatically improve both productivity and predictability when verifying their latest FPGA design.

System Context
Targeting a Xilinx Virtex FPGA, the design implements a next-generation high-definition TV Warp processor that performs realtime 3D video effects. The complete system design includes multiple high speed DSPs and a control microprocessor to perform complex video processing for a new product within Ross Video’s Synergy MD Series of multi-definition production switchers. The DSPs and multiple FPGAs interact at high speed with a DDR memory buffer to create the video warp transformation.


Key Challenges: Time-to-Market and Verification Predictability
The Ross Video team was motivated to use a new verification methodology for the design in order to reduce time-to-market, and improve verification predictability. Previously, the company had used hand-generated directed tests with C and C++ models of video-processing algorithms. This approach verified the video data path well, but it didn’t provide sufficiently high coverage of control logic, resulting in many functional failures in the lab that were difficult to probe and debug. Each test took about half a day for development, with about 15 tests developed initially.

Additional time was required to diagnose lab failures. RTL bugs were routinely found during lab testing, after which a register dump of the FPGA was fed back into the simulator for diagnosis. Bug detection, diagnosis and process retesting would typically take between one and three days. On occasion, up to 40 such iterations were needed, so the whole process could take up to four months to complete. The iterative nature of this lab-based diagnosis process greatly reduced the predictability of verification schedules.

Constrained-Random Verification
The Warp MD design included significantly more complex control logic than previous designs, presenting both new challenges and new opportunities to the verification team. “For the Warp MD project, we needed a new verification methodology to handle the increased complexity of the design,” said Ross Video’s Simon Lacroix, the hardware developer who managed both design and verification on the project.

Although Lacroix’s team had not used constrained-random verification previously, they had studied the approach and knew that it promised to be the ideal way to address the verification issues presented by the Warp MD design. “I became convinced that this was the right approach,” said Lacroix. “Unlike in previous video processing designs that were more datapath intensive, this new chip was designed primarily for data transport using proprietary protocols, and it was more suitable for constrained-random tests.”

Ross Video worked with both asynchronous and synchronous interfaces on each DSP: a processor interface and a gigabit interface. “Since we had so many entities interacting with the FPGA through many interfaces, it was really helpful to make use of constrained-random verification in order to cover as much access sequence and interaction as possible without having to write a lot of tests,” Lacroix commented. “In the end, it saved a significant amount of time.”

A New Approach
After an extensive evaluation to find the best verification language, tools and methodology, the engineers at Ross Video decided to use SystemVerilog for testbench automation with Synopsys’ VCS Native Testbench (NTB), and to implement the VMM methodology, documented in the Verification Methodology Manual for SystemVerilog. They determined that the VMM methodology provided a clean, modular and elegant approach to verification and that it could be quickly deployed.

“The VMM book provided good advice for setting up many aspects of the environment,” Lacroix said. “So we decided to follow it extensively.” The team quickly created a robust verification environment utilizing the VMM methodology’s built-in self-checking, scenario generation, transaction-level channels, transactors, and messaging services. For checking, they also made extensive use of SystemVerilog assertions (SVA), both custom-written and selected from the Synopsys SVA assertion-checker library, and then added functional coverage using cover properties.

At first, about half of the bugs were found in the verification environment and half were found in RTL. It took around three weeks to get the initial verification environment running. The Ross Video team initially had some difficulty debugging the environment, but the VMM methodology’s standardized messaging service provided them with a standard means of generating, formatting, and filtering messages that enabled both design and environment issues to be quickly diagnosed without having to use the waveform viewer.

Several of the design bugs found by the new environment were in very complex arbitration logic that would have required extensive lab debug resolution time had a purely directed-test approach been used instead of assertions and constrained-random simulation.

Lacroix commented that, “The previous testbench was not verbose with error messages, so it was hard to diagnose the problem from the error message. The VMM log file, on the other hand, was very helpful in diagnosing errors so that we could resolve issues quickly.”

In the end, the VMM methodology helped the team create a good, well-structured, scalable testbench, which helped to make the verification process more predictable. Even as new users of constrained-random verification and SystemVerilog, adopting the VMM methodology allowed the team to finish verification about a month ahead of an already aggressive schedule. “Having to create a framework like the one offered by VMM from scratch would have required a significant investment in time that our schedule didn't allow,” Lacroix noted. “The VMM provided us with a good foundation and guidelines that, in the end, made it possible for a small design team such as ours to efficiently move into a new methodology using SystemVerilog. All that was achieved in a reasonable timeframe. Deciding to use the VMM methodology was the best thing we could have done.”

About Ross Video
Ross Video designs, manufactures and supports a wide range of innovative products for use in broadcast, distribution, live event and production applications. Ross products are used to produce and distribute video and audio signals in over 100 countries daily. Ross' award winning product line includes the Synergy SD, Synergy MD and MD-X Video Production Switchers, openGear, RossGear and GearLite Terminal Gear, Ross Routing Systems and the OverDrive Production Control System.


©2010 Synopsys, Inc. Synopsys and the Synopsys logo are registered trademarks of Synopsys, Inc. All other company and product names mentioned herein may be trademarks or registered trademarks of their respective owners and should be treated as such.


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Simon Lacroix
Simon Lacroix is a hardware developer at Ross Video who was the lead designer on the Warp FPGA project. He has been with the company for four years. Lacroix received a Bachelor’s degree in Computer Engineering at the University of Ottawa, Ontario, Canada.
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  WEB LINKS

- Ross Video

- VCS Native Testbench

- Verification Methodology Manual for SystemVerilog

- SystemVerilog
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"The VMM methodology provided a good, well-structured, scalable testbench, which helped to make the verification process more predictable."