Innovative Ideas for Predictable Success
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Spotlight Enhancing Performance, Power and Yield
Smaller geometries introduce new challenges for designers, and so it is important that designers have access to the tools they need to overcome them. With this in mind, Synopsys and TSMC have maintained an ongoing collaboration that resulted in a recently announced version 7.0 of the TSMC Reference Flow. Paul Lai, Group Manager Strategic Alliances, Synopsys, and Edward Wan, Senior Director of Design Services Marketing, TSMC, talk about the how the flow has been improved to address the ever-changing needs of their customers.

For designers undertaking 65nm design, power management and design for manufacturing are becoming as important as traditional timing and signal integrity challenges. Flows must be continually enhanced to ensure that low power-optimization, statistical analysis and advanced yield technologies provide optimum silicon performance with high predictability.


Figure 1: Evolution of the TSMC Reference Flow

What's New?
TSMC Reference Flow 7.0 introduces further improvements for low-power. Its new low-power design capabilities within Synopsys' Galaxy design platform include power domain specification and verification at the RTL level, concurrent multi-corner/multi-mode optimization for multi-voltage designs, coarse-grain multi-threshold CMOS (MTCMOS) logic for leakage mitigation, and dynamic voltage-drop analysis considering MTCMOS rush currents. Additionally, power management encompasses a voltage scaling capability supporting multiple voltage islands. The combined power closure solution from TSMC and Synopsys underpins the most advanced power management reference flow in the industry.

The updated Reference Flow also has new capabilities for enhancing yield during design, including implementation support for 65-nanometer design rules, critical area analysis (CAA), and chemical mechanical polishing (CMP)-aware model-based metal fill for optimal results in metal thickness.

The inclusion of Synopsys' IC Compiler next-generation physical implementation within the Reference Flow 7.0 is central to the delivery of the new low-power and yield capabilities that address 65-nanometer design challenges.

Solid Foundation
Synopsys' existing production-proven low-power design methodologies are included in TSMC Reference Flow 7.0: clock gating, power network synthesis, power-aware placement, low-power clock-tree synthesis, multi-threshold leakage power optimization, and static/dynamic voltage-drop analysis. Synopsys' PrimeRail solution is a full-chip dynamic voltage-drop and electromigration (EM) analysis solution that enables power network sign-off in Synopsys' Galaxy™ Design Platform and delivers accurate modeling of memories and analog circuits.

The TSMC Reference Flow has also consistently focused on achieving a fast volume ramp in consideration of shorter product lifecycles. To achieve this, TSMC set out to enable the information flow between design and manufacturing, introducing specific measures to improve yield at 65nm. These included 65nm design rules, such as the Line End Rule and Zig-Zag, and a rule dummy metal fill utility, which provides better density uniformity and better insertion rate in the low density areas with multiple metal fill patterns. Half track wire spreading was also introduced, providing a more even distribution of wires, to reduce coupling capacitance and critical areas.

To improve yield, the Reference Flow aims to ensure that manufacturing issues are considered before and throughout the design cycle. Reference Flow 7.0 incorporates a complete Synopsys-based RTL-to-GDSII solution utilizing the Galaxy Design Platform for RTL synthesis, physical implementation and sign-off, and the Discovery™ Verification Platform with VCS® and HSPICE® for RTL verification and circuit simulation. As an integral part of the reference flow, extensive Galaxy support includes Design Compiler® logic synthesis solution, Power Compiler™ multi-voltage power management solution, Leda RTL Checker, DFT MAX 1-pass test synthesis solution, Jupiter-XT™ physical planning solution, IC Compiler physical implementation solutions, PrimeTime and PrimeTime SI static timing and signal integrity sign-off solutions, PrimeRail power network sign-off solution, PrimePower and PrimeTime PX full-chip power analysis solution, Star-RCXT extraction solution, Hercules™ PVS physical verification solution, and TetraMAX® automatic test generation (ATPG) solution. In addition, Synopsys Professional Services provides expertise in chip implementation and flow deployment services with Reference Flow 7.0.

Synopsys' IC Compiler next-generation physical design system unifies physical synthesis, clock tree synthesis, routing, yield optimization, and sign-off correlation to deliver unmatched design performance and designer productivity. IC Compiler provides the physical design capabilities in the Reference Flow and supports TSMC's 90nm and 65nm recommended design guidelines. It enables designers to place and route high-performance, complex and challenging designs while delivering excellent QoR with reduced design cycle time and addressing physical effects like crosstalk, IR drop and electromigration.

Ongoing Collaboration
Synopsys and TSMC's ongoing relationship has enabled the two companies to keep abreast of new technological developments. By continually evaluating changing design needs, the partnership has helped to minimize risk and improve time-to-volume for its mutual customers.

The partnership has previously worked on linking together TSMC's advanced processes and libraries, and Synopsys' design platform and expertise in chip implementation and flow deployment services to deliver the full benefits of TSMC's advanced technology features. The last iteration of the Reference Flow brought enhanced library access, so that TSMC's standard cell and I/O libraries have become available through Synopsys DesignWare Library, with Synopsys support. DesignWare Library arithmetic generators are used to provide special cells with improved quality-of-results.

More recently, TSMC has been working with Synopsys on variation-aware design. For example, TSMC has verified the accuracy of Synopsys' statistical analysis solution. Furthermore, TSMC and Synopsys are accelerating time-to-production by collaborating closely on DFM technologies to enhance advanced design flows. Synopsys' new PrimeYield solution uses TSMC's DFM information to analyze yield problems and drive implementation tools to fix those problems.

Synopsys and TSMC's ongoing collaboration has also succeeded in achieving global optimization of process technology, library, design automation, and design methodology. This approach will continue to help address the issues that create yield problems in 90- and 65nm processes, and beyond. Synopsys Professional Services also provides expertise in chip implementation and flow deployment services with Reference flow 7.0

About TSMC
TSMC is the world's largest dedicated semiconductor foundry, providing industry's leading process technology and the foundry industry's largest portfolio of process-proven library, IP, design tools and reference flows. The company operates two advanced twelve-inch wafer fabs, five eight-inch fabs and one six-inch wafer fab. TSMC also has substantial capacity commitments at its wholly owned subsidiaries, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. TSMC is the first foundry to provide 65nm production capabilities. Its corporate headquarters are in Hsinchu, Taiwan.


©2010 Synopsys, Inc. Synopsys and the Synopsys logo are registered trademarks of Synopsys, Inc. All other company and product names mentioned herein may be trademarks or registered trademarks of their respective owners and should be treated as such.


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Edward Wan, Senior Director of Design Service Marketing, TSMC
Prior to joining TSMC NA, Edward Wan held many leadership roles in the industry, including CEO of Spike Technologies in Milpitas, VP of Worldwide Field Engineering at UMC in Sunnyvale, VP of Spectrum Services at Cadence in San Jose, and VP of Worldwide Customer Engineering Operations and North America Engineering at LSI Logic in Milpitas. Mr. Wan earned a B.S. in Electrical Engineering and Computer Science from the University of California, Berkeley.
Paul Lai, Group Manager Strategic Alliances, Synopsys
Paul is a veteran in the EDA industry with over 15 years experience. Prior to Synopsys, he held various management positions in applications, marketing, and strategic programs at Gateway Design Automation, Cadence, and Viewlogic. Currently, he manages the Synopsys strategic alliance program with key foundries, such as TSMC. Paul earned B.S.E.E. and M.S.E.E degrees from Texas A&M University and an MBA degree from the University of California, Berkeley.
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"Flows must be continually enhanced to ensure that low power-optimization, statistical analysis and advanced yield technologies provide optimum silicon performance with high predictability."