| Partner Solution|
Delivering Low-Power and DFM for 90-Nanometer Designs
The move to 90nm process geometries presents new challenges that must be overcome to ensure fast time-to-market with minimal risk. Jason Sheu, Director of Design Services at SMIC, and Paul Lai, Group Manager Strategic Alliances, Synopsys, discuss Reference Design Flow 3.0, the product of an ongoing collaboration between the two companies that is geared towards addressing customers’ design needs at smaller geometries.
Since 2000, Semiconductor Manufacturing International Corporation (SMIC) has been serving the manufacturing needs of the burgeoning Chinese electronics market from its 8-inch fab facilities. To maintain an edge over its competition, the Shanghai-headquartered pure-play IC foundry has anticipated the move to 90nm process geometries and accommodated it through a strong focus on R&D as well as strategic technology and manufacturing partnerships.
Reference Design Flow 3.0 is the result of one such partnership – it has been developed and deployed in close collaboration with Synopsys Professional Services. This complete proven RTL-to-GDSII flow is geared towards ensuring that the success of complex system-on-chip (SoC) designs is as predictable as possible: it is focused squarely on shortening time-to-market and reducing risk by addressing critical timing, while incorporating a broad range of automated low-power and design-for-manufacturing (DFM) capabilities.
Low Power Focus
These last two concerns – low power and DFM capabilities – are the primary focus of the latest iteration of Reference Design Flow.
The ability to minimize power dissipation is a key requirement for virtually all application domains. By moving to smaller process geometries, dynamic power is reduced. However, without taking the right measures, static power consumption can be increased because of leakage current. Reference Design Flow 3.0 includes advanced low-power capabilities, specifically aimed at minimizing leakage power.
The advanced low-power capabilities include level shifter and isolation cell insertion and cell placement optimization, voltage area creation, multiple voltage power mesh creation, multiple voltage-aware CTS and multiple voltage-aware physical verification, Which can reduce dynamic power and leakage power dissipation significantly.
All of these capabilities were validated using SMIC's low-power design kit, which consists of a level shifter, isolation cell and clock gating cell.
Figure 1. SMIC-Synopsys Reference Flow v3.0
Enabling Design For Manufacture
DFM features include via optimization, as well as filler cell and filler cap insertion. Advanced test capabilities in the flow reduce test data volume. Reducing the volume of test data required to test the chip after manufacturing means that less time is required on the test equipment, which can dramatically reduce the cost of test.
Design for manufacture assumes higher importance at 90nm and below, as finer process geometries demand more careful treatment to enable the entitled yield to be achieved. Addressing manufacturing issues during the IC design phase can help control cost, and even save time in the production process.
There are many technology issues that together determine the eventual yield of a manufactured device. Examples of yield loss mechanisms include defects in the silicon due to random particles, problems with vias, and defects that arise during processing.
Design Flow Validation
SMIC’s low-power process and the reference design flow were validated using multiple voltage standard cell libraries, low-power design kit, memory compiler and I/O. Advanced closure features in the flow target concurrent timing, power optimization and signoff, including signal integrity (SI) prevention, analysis and repair.
The flow also has advanced hierarchical floor-planning capabilities that support hard-macros and soft-macros. This feature enables design for reuse and provides efficient support for very large and complex designs, which can be managed hierarchically.
Reference Design Flow 3.0 is based on the Synopsys Galaxy™ Design Platform solutions for RTL synthesis and test, physical implementation and signoff, as well as the Discovery™ Verification Platform and SMIC's advanced 90nm process. It is derived from the design flow in Synopsys' Pilot Design Environment and can be extended and enhanced by designers to address design-specific requirements.
As chip designers move towards more advanced designs, the partnership of SMIC and Synopsys Professional Services will continue to focus on achieving the aims of the latest iteration of Reference Design Flow: reducing risk, improving time-to-market and ensuring predictable success for chip designers.
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