| Technology Update|
Bringing DFM into Design
Addressing manufacturing issues during the IC design phase can help control cost, and even save time in the production process. Rahul Kapoor, senior marketing manager, Synopsys, explains how Synopsys’ yield analysis tool suite, PrimeYield, brings design for manufacturing capability into the design realm to accelerate time to entitled yield.
Targeting new manufacturing process nodes such as 90nm and 65nm brings clear benefits to design teams in terms of improved performance and reduced part cost. However, with the transition to smaller process geometries, it is critical that these benefits are maintained and not lost because of protracted design and manufacturing cycles and poor yield. While the increase in design and verification cycle times at small geometries is well documented, the bulk of the cycle time and cost incurred in progressing from concept to volume production is in the manufacturing and test phases (Figure 1).
Figure 1: Cost time profile for 90nm process
Need to Accelerate Time to Entitled Yield
Without an effective design for manufacturing strategy, the key problem of addressing yield issues is handed off to the semiconductor manufacturer with the GDSII. Fixing the problems that reduce chip yield requires more time (and money) to be spent during the manufacturing phase.
What has become increasingly apparent is that an integrated solution, which anticipates yield issues during the design phase, is required in order to ensure a smooth path through manufacturing. Effective DFM must span the entire design-to-silicon flow and use best-in-class capabilities. With this approach, manufacturing costs can be controlled and there is a much better chance of meeting reduced market windows.
The aim of the production process is typically to reach the entitled yield level as quickly as possible. Entitled yield is a term that is used commonly in manufacturing. As the process matures, the yield that is achievable will improve to a certain level – the entitled yield. In practice, it won’t be as high as 100 percent because there will always be some defects that cannot be prevented – for example, due to random particles in the manufacturing environment.
Sources of Yield Loss
There are many technology issues that together determine the eventual yield of a manufactured device. Examples of yield loss mechanisms include defects in the silicon due to random particles, problems with vias, and defects that arise during processing. For example, CMP – or chemical mechanical polishing, must be carefully controlled in order to prevent over-polishing. Similarly, the lithography process raises printability issues at geometries which are less than the wavelength of light – i.e. what the designer actually intended may not end up printed on the silicon. Manufacturing issues can also arise just from variations that occur during production, for example in temperature, mechanical equipment vibrations and so on. These types of problems are in general difficult to model deterministically and a probabilistic approach is called for. There is a need to develop an understanding of all these issues and the potential variations, and then address them where possible during the design phase.
By way of example, via-related issues must be tackled at various phases throughout the design process. During physical design, the router needs to be aware of where the vias will be located and whether sufficient area is available to support different via options. With this information the router can make choices that will help mitigate yield problems. Post-routing, physical verification with Synopsys’ Hercules will ensure that via coverage is sufficient across all the layers in the design.
Synopsys DFM Strategy
Synopsys has established a technology leadership position in design for manufacturing with TCAD solutions and optical proximity correction (OPC) capabilities that have market leadership in their fields. For example, Synopsys Proteus OPC is used by the leading foundries and IDMs for mask synthesis of over 80 percent of all manufactured silicon. With Synopsys’ best-in-class solutions in design implementation, what’s now required is a capability to bridge the design and manufacturing domains.
Introducing Synopsys PrimeYield
PrimeYield is a yield analysis tool suite that helps designers attain better time to entitled yield during manufacturing. PrimeYield highlights potential problems so that corrections can be made before the GDSII is generated and passed to the foundry. By making these corrections before manufacturing, the eventual yield will be improved and the time to achieve the entitled yield will be significantly reduced.
The PrimeYield tool suite is comprised of three modules:
PrimeYield LCC - Lithography Compliance Checking (LCC), which flags potential lithographical errors and process-variation effects for the designer earlier in the design process
PrimeYield CMP - Model-based Chemical-Mechanical Polishing (CMP), which locates and analyzes uneven metal fill, a major source of systematic failures in advanced chip designs; and
PrimeYield CAA - Critical Area Analysis (CAA), which enables analysis and improvement of critical areas with higher probability of yield loss in the design layout.
What typically happens today is that without an effective DFM solution, modifications will be made during the manufacturing phase in order to get the yield up. As well as changing the design, it will be necessary to run through sign-off again before shipping for manufacturing – this is where a delay of several weeks can occur when the company was expecting to ship parts much earlier. With the right analysis tools and correction capabilities, many of these adjustments can be made before the design is passed over to manufacturing.
Figure 2: Accelerating Time to Yield
Printability issues, for example, can be identified and addressed at the design stage. Some design patterns are difficult to print accurately, and hence can adversely affect yield. Figure 2 shows a segment of layout from a real 65nm design. In this case, the design passed the design rules check (DRC) with no errors flagged. Running PrimeYield LCC, however, highlighted this geometry as potentially causing an open circuit (red area). With this knowledge, the designer can make an adjustment to remove the potential problem. The design in Figure 2 is actually a memory cell which means the problem, if not picked up, would have been replicated across a large part of the chip, resulting in poor yield.
Figure 3: PrimeYield LCC Find and Fix Litho Issues
Production Accurate Litho-analysis and Integration with Implementation
PrimeYield LCC uses actual foundry models of the process to simulate the full resolution-enhancement technology (RET) tapeout flow to enable it to examine layout sensitivities of the design – even at corner case conditions. Problems that can be identified include excessive line narrowing and potential line shorting to poor contact and via overlap with metal. PrimeYield LCC ranks these problems by severity and presents them to the designer for review in a familiar DRC-like format. This approach ensures a higher degree of accuracy in the analysis, compared with techniques that estimate the process performance. The production accuracy is one of the key benefits of PrimeYield. The use of actual design data from the foundry, such as the models from the OPC process, provides a level of accuracy that is intrinsic to the value of the PrimeYield tool suite. Many months spent qualifying the tool output with data from supported foundries ensure a high degree of correlation with the production process.
Other analysis approaches don’t support production-level accuracy, instead depending on approximations to the mask synthesis flow. Consequences of this simplified approach include missed hotspots and flagging false positives, which waste design time and cause unnecessary over-constraining of the design.
Another unique benefit of PrimeYield is the integration between analysis and design implementation. For example, IC Compiler can be configured to call PrimeYield after the initial layout. Correction guidance will be formulated for problems identified by PrimeYield, and automatic fixes passed to the router within IC Compiler. For custom design methodologies, the designer receives the correction guidance within the layout editor so that potential lithography issues can be taken care of prior to finalising the design layout.
It is important to identify and correct potential planarity issues on the lower metal layers before they become serious issues in the higher metal layers. Modeling planarity with PrimeYield CMP provides the designer with a thickness report which identifies poor focus across the wafer surface and excessive variations in line geometry, leading to breaks or bridging faults. If these issues are left unattended, the consequences include excessive parasitic variations and possible open circuits.
In processes that use aluminium in the metal layers, rule-based dummy fill can be used to correct potential planarity issues as it is the dielectric between the metal that is polished off, which doesn’t cause too many problems with the wires themselves. However, 65nm processes use copper in the metal layers – the polishing process can remove a lot of copper and so cause tracks to become thin. With copper processes, adding dummy fills creates excessive parasitic capacitance. There is no substitute for accurate planarity modeling, which is what PrimeYield CMP provides.
Critical Area Analysis
Probabilistic Monte Carlo simulation is employed within the PrimeYield critical area analysis tool in order to model likely areas that may be affected by random defects. These include critical areas that are tightly packed where shorting may be an issue, as well as thin lines that might break if a defect were to occur.
Yield Grading Vision
PrimeYield is a yield analysis tool suite. This means that it identifies potential problems and fixes that can be made to improve the yield. Currently, PrimeYield does not provide yield grading information. In order for the tool to give an indication of the actual yield, two PrimeYield roadmap items are of interest,.
- The first is to identify interrelated yield issues so that the impact on overall yield can be quantified. For example, if a design is uneven due to planarity issues, the likelihood is that there will also be lithography problems.
- The second is to enable yield grading. This requires correlation of the yield data from PrimeYield with exact yield figures from the foundries. Further foundry input will enable both interrelated problem identification and improved production accuracy in the future.
PrimeYield accelerates time to entitled yield, lowering manufacturing costs and enabling faster time to volume production. Correct analysis, based on production-proven manufacturing data, reduces the likelihood of false positives and missed hotspots. Correlated automation guidance passed to upstream implementation tools enables fixes to be applied before the GDSII is passed to production. Finally, PrimeYield provides complete modeling of all significant yield loss mechanisms – not just the critical areas.
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