Innovative Ideas for Predictable Success
      Volume 1, Issue 2

  NEWS  |   CALENDAR  |   PAST ISSUES SYNOPSYS.COM  |  CONTACT US


  Technology Update
Spotlight Power Planning for SoCs
Careful power planning is essential for designs targeting advanced semiconductor processes. David Stringfellow and Kevin Knapp, design consultants with Synopsys Professional Services, give guidance on best practice recommendations that can help to ensure power integrity throughout the entire design flow.

Power integrity has become a crucial part of the system-on-a-chip (SoC) design flow because power-related issues can affect chip timing and even lead to complete device failure. Specifically, excessive rail voltage drop ("IR-drop") and ground bounce can create timing problems and electromigration effects that impact a chip’s performance and reliability.

Assuring Power Integrity
A design’s power integrity can be assured in two ways: through good power-network planning and synthesis, and by accurately analyzing the design to detect problems. The planning and analysis steps should not be regarded as isolated tasks, however, because they need to be an integrated part of the overall design flow and well understood early in the design process.

A good power-grid design and sufficient number of VDD and VSS pads limit the effects of IR-drop and other power-related issues. However, determining the feasibility of a power-grid design and the correct number of pads requires early analysis. Unfortunately, this analysis is usually required before basic design data becomes available.

Power Planning Overview
Before considering specific power integrity methods, it is useful to start with the basics of power planning. The primary objective of power planning is to ensure that all on-chip components (blocks, memory, I/O, etc.) have adequate power and ground connections. The following terms describe the basic elements of the power network (Figure1):

  • Power pads to supply power to the chip.
  • Power rings which carry power around the periphery of the die, around a standard cell’s core area, and around individual hard macros. The rings are typically in higher-level routing layers to leave lower layers for signal routing. Note that rings are also generally useful around hierarchical blocks. In some cases, these rings consume more area than the budgets allow, so design teams opt for a uniform global mesh and treat the hierarchical blocks as virtual blocks that have no physical power/ground rings around their peripheries.
  • Power rails, straps, and trunks are horizontal and vertical wires across the entire die or sections of the die. The horizontal wires on the lowest metal layer are often referred to as rails, "row straps", or "standard cell preroutes".


Figure 1: Conceptual Structures used in a Power/Ground Mesh

Power rings and straps are typically created in the higher-level routing layers. The rails and straps are usually laid out as a uniformly spaced array and then modified to allow for hard-macro power rings, wiring, keepout areas, and other restrictions. The power rails connect the standard cell power pins together and then extend to the power rings, where they are connected with vias. After the straps and trunks are inserted, they are all tied together using vias and via stacks. The rails are created only within standard cell placement areas that are not already blocked by hard macro placements or wiring keepouts.

IR Drop Effects
The resistance of the metal in this power distribution network causes steady-state IR drop. By reducing the voltage difference between local power and ground, steady-state IR drop reduces both the speed and noise immunity of the local cells and macros. Further, dynamic IR drop occurs when the simultaneous switching of on-chip components causes a dip or spike in the power/ground grid. The current pulled by simultaneously rising edges leads to a dip in the power grid, while a similar phenomenon on falling edges leads to a voltage spike on the ground grid. These phenomena are sometimes referred to as power bounce and ground bounce, respectively, and they reduce the logic gate noise margins. The resulting functional failures or timing errors are extremely difficult to anticipate with traditional signal integrity and timing analysis.

Electromigration Problems – and Solutions
Electromigration occurs when large current densities cause a flow of metal atoms from the negative to the positive-biased end of a length of interconnect. This flow can result in catastrophic failures by either creating voids (opens in the metal line) or extrusions (shorts with neighboring metal lines). Electromigration has become a greater problem as interconnect dimensions shrink, causing current densities to rise. The tall-and-thin aspect ratio of today’s interconnect also adds to this problem.

Electromigration problems in power meshes can be avoided by meeting the maximum current density limits for the process (as documented in foundry layout guidelines). When calculating the metal width required, bear in mind that straps wider than the process slotting size will be slotted at some point in the design process, thus reducing their conductivity.

Early, Accurate Analysis Vital
Power planning is now a critical part of the overall design planning process. Power consumption and special power requirements are among many considerations that dictate the placement of cells in a floorplan. For example, some flash memory has a high-voltage programming input that must be within a certain distance of an I/O pin. These mandatory requirements should be addressed first.

In fact, developing the power structure early helps avoid many problems in the rest of the design flow, and early, accurate analysis is essential. If analysis is put off until late in the flow and the number of power and ground pads must be increased, for example, the additions may cause the design to become pad limited.

Similarly, because power structures consume physical area that affects the floorplan and signal routing, inserting power structures after floorplanning can force floorplan changes. The power grid topology also affects placement and signal routing within child blocks and so should be in place immediately after top-level synthesis and prior to final child-block partitioning.

Power Needs Drive Floorplanning
Floorplanning helps avoid IR drop and electromigration problems through strategies such as placing the most power-hungry blocks near the periphery of the die and preventing concentrations of such blocks in any one area. Even if power consumption were spread evenly over the entire chip when viewed from the block level, IR drop would still be worse in the center of the chip because of the increased wire length. IR drop in the center of the chip causes the logic there to run slightly slower, and this effect becomes more important in overall timing as threshold voltages decrease.

Some wires in the mesh carry more current than others, so the current on every wire, junction and via should be calculated. Vias that are not big enough act like fuses, ready to blow when the current is too high, so via arrays should be analyzed for IR, current density and electromigration.

Calculating the power dissipation at the block level throughout the design process is important to determine whether the design is meeting the specified power budget and to estimate the size of the power grid. Early in the design process, manual calculations or spreadsheets are often used to estimate power; as the RTL matures, design tools can be employed to refine power estimates. In the initial stages, power estimate accuracy within +/-30% of the post-layout figure is a reasonable target. As the RTL migrates to gates and transistors, the power estimates can be further improved. For final power signoff of the floorplan, the actual netlist, the net switching activity corresponding to typical operating scenarios, and annotated parasitics should be used.

Creating the Power Structures
Recent enhancements to floorplanning tools such as Jupiter XT make it possible to synthesize the power grid based on chip power and voltage drop requirements. Some older floorplanning tools insert power and ground rings, and the designer must specify their width and spacing. In this case, a good rule of thumb is to assume that each side of the ring must carry a quarter of the design’s current. To get this value, divide the overall power budget by four and convert to current using the core’s primary voltage. The allowed current density for the metal layer(s) used for the rings can then be used to determine the required width. If possible, this width should be limited to avoid the need for metal slotting.

Power and ground rings should be created around any hard macro to enable orientation independence and eliminate the need for the chip’s power structure to conform to the macro’s power structure. Fortunately, most library vendors are now producing hard macros with internal power and ground rings. This practice improves the quality of the IP and simplifies top-level power grid planning. For any hard macros that do not include rings, the same quarter-current rule of thumb can be used to determine the width of the rings.

Once the power rings have been established, power and ground must be routed to the standard cell rows. Abutment of the cells accomplishes some of the connections. The floorplanner is used to add additional rails aligned with the power rails inside of the standard cells. The lowest horizontal metal layer should be used for these additional rails. Some technologies and/or floorplans make it necessary to insert filler cells temporarily to get a complete grid. After insertion of the rails, the filler cells are removed.

The floorplanner makes the rail spacing consistent with the standard cell height, but the user must specify rail width, most often using network synthesis tools that are aware of the process geometries. With the usual mirrored placement rows and their alternating power and ground rails, the width of the additional rails is larger than the width of the straps within the cells. Typically the rail width and spacing increase at each successively higher metal layer. Wider rails can be used in the lowest metal layers, but they often result in the standard cell rows being spaced further apart and therefore reduce the placement area and signal routability.

The straps and trunks that distribute power across the chip offer designers more flexibility than rings and rails and represent the most important means to address specific IR drop issues. Designers must determine the appropriate spacing, width, and layer of these straps and trunks. Note that it is usually better to use many thin routes (rather than fewer wide routes), especially in the lowest metal layers, to improve overall routability.

Summary
Careful power planning and analysis is important whatever the target technology, but is critical for process geometries of 90 nm and below. Starting power analysis early helps to avoid potential problems from occurring in the later stages of the design flow. The best practice recommendations described here have been developed and proven through multiple 90 nm implementation projects and offer a starting point for power planning and analysis in SoC designs.


©2010 Synopsys, Inc. Synopsys and the Synopsys logo are registered trademarks of Synopsys, Inc. All other company and product names mentioned herein may be trademarks or registered trademarks of their respective owners and should be treated as such.


Having read this article, will you take a moment to let us know how informative the article was to you.
Exceptionally informative (I emailed the article to a friend)
Very informative
Informative
Somewhat informative
Not at all informative

Register Buttom

Email this article

About the Authors

David Stringfellow
David Stringfellow is a Staff Consultant at Synopsys Professional Services specializing in low-power design, physical synthesis, rail analysis, SI noise analysis, and timing closure. He has worked on designs including automotive engine controllers, x86 processors, wireless handhelds, and HD television chipsets. He earned BS and MS degrees from Purdue University, holds four U.S. Patents, and is a General Motors Fellow. He is a Synopsys Distinguished Author and has been with Synopsys for six years.
Kevin Knapp
Kevin Knapp is a Senior Design Consultant at Synopsys Professional Services specializing in design flow methodologies, physical synthesis and timing closure. He has led design flow and methodology development, and has worked on SOC designs for the wireless, DSP, networking, communications, and storage industries. He received his BS with honors from the University of Illinois, holds a U.S. Patent, is a Synopsys Distinguished Author, and has been with Synopsys for over seven years.
Horizontal
  WEB LINKS

-   Synopsys Professional Services

-   White paper: "Design Planning Strategies to Improve Physical Design Flows — Floorplanning and Power Planning."

-   White paper: "Power Management in Complex SoC Design."

-   White paper: "A Practical Methodology for Calculating Acceptable IR Drop Targets in Advanced VDSM Design."

-   White paper: "Power Integrity for SoCs: Power Planning and Signoff Flows."
Horizontal
"…developing the power structure early helps avoid many problems in the rest of the design flow, and early, accurate analysis is essential."