Innovative Ideas for Predictable Success
      Volume 1, Issue 3

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Spotlight Designing Winning Products
The purpose of the silicon business is to make money, but many chip designs fail to achieve this goal. Paul Keswick, Executive Vice President, and Nagendra Cherukupalli, Vice President, from Cypress Semiconductor, reveal the secrets of how to stimulate winning product designs through sustained innovation and discipline.

A winning product is a product that both fulfils customer expectation and generates a big return on investment. There are some best practices that can be followed to create an environment in which winning products are created routinely.

Innovation
The first step is to cultivate innovation within the company. Although designers can have innovative ideas sporadically, a sustaining process is needed to trigger innovative thinking all the time. And these ideas need to be harnessed within the context of product constraints viz., cost, schedule and resources. Clearly defined product constraints challenge designers to innovate. This ensures that the idea that they come up with has high impact to the program they are working on. All engineers are given the opportunity to participate in this process, from the grass-roots level upwards.

At Cypress we have created a culture where innovation is recognized and rewarded. Recognition comes from top management directly hearing these ideas from the innovators. Reward goes to the team working on the idea, not just to the individual, and thus fosters a culture of teamwork.

At Cypress, this is referred to as the Design Productivity Initiative. It has been in practice for over two years, and has made a significant difference for us in terms of cost savings, improved cycle times and healthier team spirit. As part of the initiative we provide an opportunity for engineers at each of our design centers to present directly to our senior management the latest innovation they have created in the context of the product they are working on. Each idea has the opportunity to be declared as a "design productivity win" when it saves a certain amount of dollars to the corporation or cuts down the cycle time by a certain number of weeks. Every quarter one such idea is presented to the CEO in the boardroom by the innovator. This level of recognition motivates engineers a lot more than just the monetary reward that goes with it!

Tackling Cycle Time
At Cypress, we aim to create a set of products that meet customer requirements within a market window. A constraint we face all the time is that the design systems and design methods are so complex that the individual designers have to deal with multiple tools, design rules, numerous simulation, manufacturing issues, marketing requirements, and so on.

Although designers can benefit greatly from the flexibility and ease of use that individual tools provide, it isn't cost-effective to custom-build tools for each individual product. To solve this problem, our methodology is to derive a specification for a family of products, instead of targeting one single product. We then use the traditional design system to come up with a base product, which we call a platform product, and then design derivatives rapidly by using a custom software solution.

This is an approach that Intel and other companies have used successfully for a number of years for their microprocessor architecture.

The platform product has to be forward extensible. Designers can keep growing the capability of the chip by adding more functionality, but without breaking backward compatibility. This ensures that applications that worked before will continue to work even after the extensions have been put in place. Through creating a 'platform EDA' custom software solution, it is possible to create a number of derivatives from the platform product rapidly.


Figure 1: Cypress Platform Methodology

An additional benefit is that the IP developed for the platform product gets a lot of reuse and thus amortizes the cost of development across multiple derivatives.

Halving Cycle Time
One Cypress design team working on a set of timing products has been challenged to drive down the spec-to-samples cycle time from 10 weeks to just 2.5 weeks, starting with the base die and ending up with a number of derivatives. This is an extremely aggressive target, as it includes the design, verification, manufacturing and test times. The means of achieving this cycle time reduction is by using the platform approach that allows the design team to focus on a family of parts from the get-go.

The custom EDA solution developed to achieve the cycle time reduction includes two modules one that provides an early view of the final manufactured part and ensures that the part is manufacturable. The other module helps automate the full chip customization, assembly and verification. This customized platform EDA product enables the design team to generate multiple derivatives from the same platform product in significantly reduced design cycle time.


Figure 2: Platform EDA

The cycle time ratio for development of six derivatives can be halved, compared with the individual development time for each derivative:

Cycle time ratio for 6 derivatives = (10*6)/(2.5*6 + 15) = 2

Multiplying six designs by ten weeks, the length of time we expect it would take to design each separately gives us the total time for the 6 parts. 2.5 weeks is the cycle time target for each derivative post creation of the software. Multiplying 2.5 weeks by six derivatives, and adding 15 weeks overhead for developing the custom EDA software, we can calculate that the cycle time is halved.

It may be beneficial for EDA companies to partner with design companies to develop custom software for platform products. EDA companies might have to share their IP secrets and design companies might have to support EDA companies' platform learning, but there is clearly much to be gained from exploiting the combined core competencies of both parties and from reducing the cycle time for product families.

Discipline
Innovation is the first key step for driving chips forward into winning products. The second is discipline. There are a number of key factors that make for good design discipline.

Discipline should be a rigorous and repeatable process that can be applied to the development of a full spectrum of new products, ranging from memory products to logic products and clock products. At Cypress, we are taping out a new chip every week. You cannot achieve that level of productivity without discipline.

If discipline is to be practiced fully, there should be intermediate milestone deliverables on each design project, so that the progress of a design can be tracked within the context of its complete development. At Cypress we use a system that comprehends 12 milestones, each with very specific deliverables.

This process lends itself very well to measuring a number of things along the way and, by using a learning environment, practices can be improved and better results obtained.

The discipline system is instilled into the Cypress design community and is followed each day. Without it, it would be much harder for the Cypress' 450 design engineers to share their designs across the company's 18 design/CAD centers around the globe. Cypress uses a common design environment, which enables complete design portability: any designer can move from one global site to another and resume work on a design without any disruption, regardless of location.

Design Process
Creation of a business plan is the first in a series of milestones in the Cypress design process for any given project. This plan, incorporating schedule predictions and market analysis, is an important starting point in developing a winning product, and is captured in a set of documents for approval by the CEO. This ensures that the company is backing the project with investment and the team is committing to a schedule and cost.

The next step is to complete the architectural definition and external spec, before starting the schematic/RTL phase. Once the layout is complete and all the design specifications have been met, it is time to tape out. The project goes through manufacturing and 10 engineering samples are produced. Ideally, the samples will meet the datasheet parameters under all conditions without further mask changes. Then the final two milestones are passed as the product meets full qualification and is ready for transfer to volume manufacturing.

Measurement Enables Optimized Design
The milestones are useful for measuring cycles so that bottlenecks can be identified and improvements can be made. At Cypress, everything is measured very carefully and, by comparing projects, it is possible to determine where problems lie. The key indices include both qualitative and quantitative analyses of the following:

  • Project launches
  • Product introductions
  • Mask ratio per single quarter
  • Mask ratio over 4 quarters
  • Design/development cycle time (weeks)
  • Concept definition time
  • Cycle time to meet all specs with no further mask changes
  • Patent filings
  • Performance to schedule that is comparison of the actual with the plan
  • Resource utilization
  • Memos/person/week

The mask ratio is something we pay a lot of attention to. This is a measure of the quality of the design. If a design that originally specified 22 masks actually requires 44 masks to make it into production, that means we have a mask ratio of 2, which is outside of our normal limits. At Cypress we target a mask ratio of 1.2, which means that 20 percent of the masks are available for dealing with design risk. To achieve a mask ratio of 1.0, the cycle time will probably increase because we have to put in a lot more effort to make sure everything is perfect, and if a mask ratio is 2.0, that means that a lot of masks are being burned.

We also designate 20 percent of project time to allow for mistakes and cycles of learning, especially if a new platform chip is being designed. We pay a lot of attention to patents, and have around 1,400 issued in the US. We measure performance to schedule, so that we notice delays when tasks are not executed according to plan. And we also measure resource utilization. At Cypress we track every engineer to make sure that we have full visibility into exactly how they are occupied in each of the programs they work on.

Everything is documented. Because all designers are required to write a memo every two weeks, we have a comprehensive database history of their progress on each project, which is particularly useful if that designer leaves the company. The documentation also helps to protect our intellectual property by providing dated written evidence of the idea conceived by a Cypress engineer.

A key advantage in using these metrics mask ratio, for example is in conserving 'goodness'. Design behavior is improved by identifying issues and developing ways to tackle them and by preventing them from re-occurring. Checklists and scorecards serve as useful reminders for designers and program managers respectively, and review boards build confidence.

The design cycle time metric can be used to battle complexity. The metrics can be used to innovate and automate (IO ring compiler), to integrate new tools and methods (power grid synthesis), and to train designers in new approaches (low power).

Cypress spends a lot of time breaking down barriers, using metrics that focus on execution, by forecasting and dealing with issues ahead of time.

Execution Management
An important part of the culture of discipline at Cypress is 'execution management'. This includes making sure that the right team is chosen, to ensure that the right skill sets are there. If a mixed signal block needs to be designed, it is better to find someone with the relevant skill set than to assign a logic designer to this product. In fact, Cypress goes to the extent of having a product launch review board which asks a lot of questions and analyzes the construction of each team. This ensures that the individuals have the right training and skill sets, so that inexperienced engineers are assigned to parts of suitable complexity.

Cypress also checks on a daily basis that each design team has what it needs: more resources, disk drive and processor computing space, for instance. Execution management also involves creating a 'plan to win', so that all of these resources are signed off ahead of time by executive staff, including the CEO.

Managing the details of the development process and project status are key points in execution management. Every week, each design manager submits a project status report to a database, that is monitored and analyzed to make sure there is no leakage and that no skilled engineers are left on the bench. This result-focused approach means that upcoming milestones are discussed ahead of time and that teams communicate with one another so that any potential barriers can be removed.

Cypress also takes measures to keep commitments visible, on displays to remind staff about forthcoming milestones and the preparation that needs to be done for each.

A 'learning system' at Cypress reduces the chance of problems recurring. In the past, if a program got delayed by a couple of weeks, the design team would be required to explain the problem to the CEO. This serves to discourage delays. Continuous progress has meant that these meetings now only take place in the event of a catastrophe. Probing questions are asked in the event of an excursion so that the root cause can be identified and analyzed and corrective actions put in place. Focusing on exceptions and ensuring that effective corrective actions are incorporated into Cypress' methodology means that the same type of problem is unlikely to recur.

Winning Product :PSoC™ Programmable System on a Chip
This design is a good example of how programmability can be used to derive different chip configurations to suit a number of applications, from image stabilization in digital cameras to touch-sensitive TV remote controls, cell phones and click wheel control for MP3 players.

The design has configurable analog and digital blocks, 4KB to 32KB of flash memory for program storage, 256B to 2KB of SRAM for data store and an M8C microcontroller. The key value proposition is the reduction in component count, from 90 to 28 with the new design, which results in a significant reduction in bill of materials cost.


Figure 3: PSoC Chip Floorplan

Besides silicon (Figure 3), there is a full suite of software so that it can be configured to provide a whole product solution to customers. It is the software and hardware working together that actually defines the product

The key to developing this winning product is innovation in developing such a flexible specification to meet the needs of a diverse range of applications, and the discipline to bring together hardware and software expertise to build the product. Innovation and discipline working hand in hand gives us the best possible chance of developing products like the PSoC, which are successful both technically and commercially.


©2010 Synopsys, Inc. Synopsys and the Synopsys logo are registered trademarks of Synopsys, Inc. All other company and product names mentioned herein may be trademarks or registered trademarks of their respective owners and should be treated as such.


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About Paul D. Keswick
As Executive Vice President of New Product Development at Cypress Semiconductor, Paul presently manages a 600-person team across the US, Europe, China and India. Current responsibilities include managing Design, Product & Test engineering, IT, HR and Legal. His key contributions include defining and deploying new product development business processes, defining and managing design metrics, deploying and managing IT systems, and ensuring that Cypress stays on the leading edge of performance for product delivery. Paul has held various technical and managerial positions at AMD and Cypress Semiconductor. He has 27+ years of experience in IC design backed by a B.S E.E from University of California, Berkeley and an MBA from Santa Clara University.
About Nagendra Cherukupalli
As Vice President of Asia Pacific design centers and Chip Integration at Cypress Semiconductor, Nagendra presently manages a 140-engineer team across four design centers in the US, India & China. Current responsibilities include delivering on chip commitments to customers and managing the teams to success via performance to key metrics. His key contributions include starting two design centers for Cypress in India and China, and promoting Cypress brand via keynote, panels, press conferences and articles. Nagendra has held various technical and managerial positions at AT&T Bell Laboratories, Cadence Design Systems and Silicon Value, a fabless ASIC startup in Silicon Valley. He has 21+ years of experience in chip design and software development, backed by a Ph.D. in Computer Science from IIT, Chicago. He currently reports into Paul Keswick.
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-   Cypress Semiconductor
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"Although designers can have innovative ideas sporadically, a sustaining process is needed in order to trigger innovative thinking on a regular basis."
"At Cypress, we are taping out a new chip every week. You cannot achieve that level of productivity without discipline."