Innovative Ideas for Predictable Success
      Volume 1, Issue 4

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Spotlight The Value of Collaboration in Verification
George Zafiropoulos, vice president of marketing, Synopsys Discovery Verification Platform, considers the growing importance of a collaborative approach in tackling verification issues and steering the company’s verification roadmap.

The early days of the EDA industry were exemplified by largely transactional relationships between tool suppliers and design companies. Most design companies would buy the EDA tools, get training from the vendors and then deploy the tools. Integration support would be provided by the in-house CAD department, or the designers would take time out of the design cycle to set up the design environment.

Over the last several years, EDA vendors have supplied consulting services, custom IP and offered closer support models and design flows, as well as tools. This solution-based approach has been effective in helping design teams become more efficient, ensuring compatibility between different parts of the flow and economies of scale in dealing with their vendor of choice.

Today there are signs that the relationship is evolving further. Despite EDA tools becoming progressively more advanced and robust, leading electronics companies are choosing to partner with EDA vendors in much closer collaborative working and business relationships. Also in evidence is closer collaboration in other parts of the IC development ecosystem.

The challenges of designing and verifying multi-million gate chips are huge. With multiple processors, complex peripheral interfaces, executing millions of lines of code and running at very low power levels, there is little room for error. Maximizing productivity, minimizing risk and reducing time to market requires that design companies exploit all of their strengths – including their partnerships with other organizations in the supply chain.

Collaborative Verification
The verification pressures facing design teams are widely acknowledged. Shrinking market windows drive the compression of project timescales to an extent that it’s now a case of “How long do we have for verification?” rather than “How long will verification take?” The globalization of IC development means that more often than not a chip design will be dispersed across different offices and time zones. Having engineers working around the clock can boost verification productivity, but only if information and data can be shared seamlessly. What’s more, every time the number of gates on a chip doubles, the required verification effort quadruples. Adding compute resources can help to improve verification performance but, like engineers, the resources need to be properly deployed and adequately managed.

So, how can collaboration help address these pressing verification issues?

Solution Foundations
There are at least four areas where collaboration between industry participants is key to providing a basis for improved verification. These are industry standardization, methodology development, productivity and, last but not least, technology development.

Standardization
Industry standardization has been important to the development of the EDA business since its inception. Developing momentum around a standardized design language or data format benefits the development community and ultimately enables growth across the industry. This has been proven in the past with successful standards such as Verilog, VHDL and EDIF, stimulating tool and methodology innovation, enabling more complex designs to be built by trained engineers who could share a common design language.

Standardization requires collaboration between end-users and vendors (who are often competitors) within the framework of a standards body. Over the years Synopsys has dedicated significant time and resources in support of standards it believed would benefit the industry.

The evolution of SystemVerilog provides a tangible and recent case in point. SystemVerilog is vital in enabling unification of a number of fragmented verification technologies, which in turn has promoted a significant advance in verification productivity. More than 90 products and services are based around the language. The growth in use of SystemVerilog is unprecedented. Within the last year, the rate of adoption has exceeded over 200 percent as a design language and over 350 percent as a testbench language. Many leading companies have presented at Synopsys user group meetings (SNUG) on their application of SystemVerilog to achieve reduced cost and increased verification performance.

Synopsys has backed the specification with the introduction of a full SystemVerilog flow, and recently announced the donation of a library of advanced SystemVerilog assertion checkers to the Accellera standardization body.

Methodology Development
A good methodology is borne out of successful chip development projects. Like standardization, successful methodology has value for the industry as a whole. Communication of best practice has been a feature of collaborative events like Synopsys’ User Group (SNUG) for some time. Drawing together leading IC development engineers and Synopsys’ application and research engineers, problems and solutions are shared and discussed. The technical value of this forum is evidenced by the consistent growth in SNUG audiences, even in an age of instant electronic communication.

Collaboration is at the root of Synopsys’ verification methodology, not only with ARM, the joint authors of the Verification Methodology Manual (VMM) for SystemVerilog, but more fundamentally with some of the early pioneers of verification methodology.

As long ago as 1992, Janick Bergeron, now a Synopsys Scientist, worked on self-checking transaction-level testbenches while at Nortel. Continuing this work at Qualis, Bergeron devised a new approach based on highly-reusable components with transaction-level interfaces between them. With Synopsys’ acquisition of Qualis in 2004, the benefits of the technology were quickly realized and adopted as a core capability into the DesignWare® Verification IP (VIP) products, while Bergeron continued to bring his previous experience to bear in driving a collaborative approach to verification methodology. The VMM was a result of collaboration within Synopsys between the verification and reuse groups, as well as with lead customers, and with ARM providing expertise in system-level and hardware-software issues.

This original collaboration has given rise to a raft of VMM-related activity, including new books, training workshops and academic courses. In fact, it has been a catalyst for a whole new market within EDA.

Productivity
The power of the SystemVerilog language, providing a higher level of abstraction, built-in assertions and advanced testbench support has unquestionably boosted verification productivity. Other techniques, ranging from the use of formal verification to enhanced simulation performance have also contributed to improvements in efficiency. In tandem with improvements in technique, more sophisticated processes have also made a difference. The use of coverage metrics and analysis tools have provided a more systematic route to identify best practice.

The benefit of collaboration is plain to see. Synopsys is involved in many chip development projects, with customers choosing to develop a close working relationship between engineers from both sides. Leveraging our collective experience, Synopsys is well placed to identify best practices. Synopsys can help the project team or the whole company benchmark their verification technology and processes and identify opportunities for improvement.

Technology Development
At the root of the value of the EDA company is the technology it delivers. Customer input is of course critical to the product development process. In the past, this input would have been solicited by listening to customers’ requirements. Now, the process of new product definition is more active and engaging.

The benefit of working very closely with leading electronics design companies is that the next generation of capabilities can be defined more accurately and current technology can also be optimized for their unique requirements. The resultant technology benefits the whole market, across all regions, from startups to multinational organizations.

Synopsys works with many leading electronics companies to define whole new areas of verification technology. This involves taking their requirements, prototyping the products, deploying them in early form in the early adopters’ environment, and learning together what the potential is and how best to use the new technology. The benefit to Synopsys is having access to a real design environment to develop its technology and get it right. The benefit to the customer is that Synopsys delivers technology that best meets their needs, which the customer gains access to before the rest of the market.

In practical terms, Synopsys engineers will work on-site with customers, working together on the customer’s project. Effectively, the Synopsys engineers become an integral part of the customer’s engineering team, an approach which provides great insight into what is important to customers and ensures that technology is used to its full potential.

The results of this degree of collaboration are tangible and in many cases quantifiable. Working with a wireless communications company has helped to define next-generation coverage technology; collaboration with a broadband communications company helped to refine Synopsys’ Native Testbench technology (NTB) and reduced the customer’s full chip regression testing from five days to one day on a 10M+ gate design; work with a networking design team helped in the development of third-generation constraint-solver engines and enabled significant cost savings from their development process.

Verification Roadmap
While the focus of much of the collaboration is around deployment and productization of current technology, definition of the Synopsys verification roadmap presents an exciting and key challenge where customer involvement is equally important.

Synopsys’ verification platform has brought an abundance of verification technologies together around a SystemVerilog core to boost verification productivity. Collaboration has built a consensus around the pressing need to now improve predictability in the verification world. Verification engineers are faced with some key questions, which are often impossible to answer: “How much verification is enough? Have I tested everything? When can I tape out?” These are all issues that keep verification engineers awake at night and that are at the heart of Synopsys’ predictable verification roadmap. Synopsys is currently working with key customers to refine technology to help manage and predict verification tasks.

EDA’s Collaborative Future
Collaboration is essential. It helps to bring new technology to market faster, and ensure that when products are released, they properly address real problems. Collaborative efforts are at the heart of industry standards, which in turn drive the industry forward much faster than fragmented proprietary technologies would allow. Sharing best practice and recognizing blind alleys has propelled the industry forward in recent years by enabling collective experience to be codified in methodology and process.

Synopsys’ collaborative instincts are apparent in its support for all of these activities, and the company recognizes that a collaborative future is essential for the continued success of our customers.


©2010 Synopsys, Inc. Synopsys and the Synopsys logo are registered trademarks of Synopsys, Inc. All other company and product names mentioned herein may be trademarks or registered trademarks of their respective owners and should be treated as such.


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