| Industry Insight|
Implementation – Complete, Correlated and Concurrent
The Galaxy Design Platform™ is instrumental in successful design for manufacturing. Aart de Geus, CEO and Chairman, Synopsys, discusses the company’s implementation technology roadmap and explains how Galaxy based implementation flows are ideally suited to achieving yield closure.
For the past few years, Synopsys’ focus has been on the ‘three Cs’. The first C is complete: we wanted to offer a complete set of products that take designers all the way from the RTL to tapeout: including area, speed, timing, power, test and yield. Our second C is correlated: unwelcome surprises may be avoided if tools can accurately predict what will happen further on in the design process; we envisaged an ideal design flow where approximation is gradually refined in a monotonic fashion. Furthermore we have correlated all of our products, so that the same calculation engine is used for timing and power in the synthesis, in floor planning, in place and route, and in the sign-off tools. The third C is concurrent: we wanted to develop the capability to optimize everything simultaneously.
Applying the Three Cs
The three Cs have been applied right across the Galaxy Design Platform. Design Compiler, for instance, has greatly benefited from the ability to look ahead. The most recent version delivers substantial improvements – specifically in speed. It is now more apparent that there are two types of design flow: a mainstream flow for designs at 180nm and 130nm, and a very advanced flow for the new set of designs at 90nm and 65nm. Our aim has been to simplify the design flow substantially, to enable mainstream designers to work much faster, while ensuring that designers using advanced flows have all the controls they need. Design Compiler fulfils these requirements and carries excellent synthesis results into the layout.
Figure 1: Predictability – Galaxy Delivers Coherent Performance
Here’s the substantiation. Figure 1 shows that the synthesis estimate correlates remarkably well with what was actually found in the layout. With a complete flow, rather than asking if the synthesis improves, the question is whether the overall end result is better, and systematically the answer is yes. This year we also introduced topographical technology, a move away from traditional wireload models that has enabled us to predict much better in synthesis what will happen in layout. We achieve a much better timing and area correlation with topological technology: distribution of slack in the synthesis and in the layout is actually very close. Typically, compared to the final layout we expect synthesis results to be within about 15 percent on timing and five percent of area. One of the reasons that we have been able to do so well on the synthesis side is that we have significantly improved on the layout side. Much of the improvement in predictability is due to the introduction of Synopsys Galaxy IC Compiler. We took PrimeTime, our key timing signoff tool, and developed a remarkable correlation with the IC Compiler results. The correlation between the estimated parameters and the extracted data is very good. IC Compiler has provided the foundation for a flow that is substantially more productive and more predictable.
IC Compiler is a major step forward in terms of performance and low power. It has also enabled significant improvements in productivity. Across a spectrum of designs targeting different process nodes, IC Compiler has helped customers improve turnaround time by an average of 2x.This is a clear benefit from our effort to develop complete flows, rather than focusing on individual tools. We want to enhance productivity across the whole process.
Low Power Capabilities
Virtually every chip that’s designed to 65nm is now a low-power case. We have added substantial capabilities to specifically focus on power, which is very important as people move to new tools and the new methodology at 90-nm and 65-nm. We support a number of techniques for optimizing power: selecting different supply voltages, turning various portions of the chip on and off, and using variable voltage supplies and supporting multiple voltage areas. With our partner ARM, we’ve also worked on solutions to enable changing the voltage dynamically, under software control, as a function of the processor.
At Synopsys, we know almost every chip in the world since most use our synthesis tools, So we are able to track the most advanced designs. A low cost cell phone chip recently finished by an Asian company used a multi-voltage strategy and achieved 10 percent better power consumption, with a two week improvement in turnaround time. Working on a very complex ultra-low power multimedia processor targeting a 90-nm process, ST Microelectronics was able to achieve timing closure 3x faster than before, despite implementing a complex low-power, multi-supply design. Both companies used a Galaxy low-power flow.
The Impact of Smaller Geometries
Analysis of the number or active chips and tapeouts at 90-nm and 65-nm show that over a period of one quarter, the number of tapeouts at 65-nm rose from about 20 to 52, signaling a sudden surge in development on this process node. As a matter of fact, a number of customers have said that their move to 65-nm is happening more rapidly than they had anticipated – because they require the integration levels that 65-nm offers to support increased product functionality. Interestingly enough, more of the wireless design teams are using these advanced technologies quite successfully.
At 90-nm and 65-nm, simply achieving a successful tapeout is no longer good enough. The chip must also ‘work’ in terms of providing the required yield and capacity. It is important to look at all the things in design that will impact yield, notably in design for manufacturing, where yield challenges are increasing.
The fundamental challenges with designing for smaller geometries are due to physics ‘bubbling up’ into the design domain. Over the last 40 years, the solution for getting better yield has been to make designs smaller. With a fixed defect density in silicon, reducing the geometry size minimizes the chance of encountering a defect.
However, advanced copper interconnects have more serious reliability characteristics than the aluminum interconnect used in previous process generations. Thermal cycling causes voids to develop in copper interconnects as a way to reduce the tensile stresses that develop in long interconnects. The voids form preferentially at the bottom of vias – making vias the number one cause of yield and reliability issues. Designers consider adding redundant vias, on the basis that if one doesn’t work, another one might. However, this course of action results in additional capacitance and area. The question is, how can you optimize the vias without giving up on timing, area and power?
Advanced Manufacturing Techniques
Chemical mechanical polishing (CMP) is one approach to yield improvement. It is used to keep a lithography surface flat (or planar) – including both aluminum and copper metallization. Originally, this planarization was a yield enhancement technique.
Today, however, CMP can pose a yield challenge. CMP removal rates are a function of local interconnect density. Therefore, CMP will create thickness variations of the intermetal dielectric or of the copper interconnects. To avoid these problems, many manufacturers began to insert dummy metal fill to even out the interconnect pattern density. The dummy metal fill, consisting of tiles in empty areas of chips, is inserted in a post-processing step.
With smaller geometries, the photolithography becomes very complex. If you use light at a wavelength of 193nm and you go to a 65nm process, you need to make a lot of corrections to your mask in order to achieve the correct final layout. Reticle enhancement technology (RET) is probably one of the most rapidly growing areas of complexity, and is the key reason why masks are becoming so expensive.
Working with smaller sizes also means that we get more and more variability on the wafers, and also within a chip. As a result, we have started to add more statistical distributions in the calculations that we do. The physical world is a statistical world, so it adds a lot of complexity in the calculation, but the addition of statistical distributions is a substantial help, and we have already seen some very promising results.
Figure 2: Critical Area Optimization
Lately, we have also been applying ‘critical area optimization’ to design, which means looking for defects that could cause short circuits or open circuits to occur. The graphs in Figure 2 are notable: they show that our ability to predict what will happen is remarkably strong against the reality. This is just one of many yield optimization tricks or techniques within the layout system that we have developed.
Figure 3: DFM Expertise in Galaxy Detects and Corrects Lithography Hotspots
We are also introducing numerous techniques which relate to mask-making. We can perform a lithography-compliance chip analysis where we are looking at hotspots. If you just stuck with the layout in Figure 3, you would find a hotspot. We have built into the layout system the ability to correct for those to produce a cleaner layout. Many of these techniques interact and, in doing so, interact with the actual reality of timing, area and power.
These developments mean that some tasks can be performed automatically and kept out of the design sphere, enabling designers to focus on achieving a functionally-correct implementation.
Closing the Loop
Over the last three years, we have been able to develop and have accumulated a unique collection of technology which enables yield closure to be reached. We have developed a selection of library elements in synthesis: optimization functions in IC Compiler, provide compliance checking and physical verification capabilities. By way of example, Synopsys is one of only two companies that provide reticle enhancement technology, and we are also a leader in fracturing products.
The objective underpinning our strategy is to close the loop. How can we help optimize yield from a design point of view? Our aim is to do for yield what we are able to do for timing: predict it well enough to make decisions in the design phase to have a positive economic impact because your chip is yielding well in manufacturing. And already this year, we are seeing accelerated success across a number of customer designs that are using our Galaxy implementation flow.
©2010 Synopsys, Inc. Synopsys and the Synopsys logo are registered trademarks of Synopsys, Inc. All other company and product names mentioned herein may be trademarks or registered trademarks of their respective owners and should be treated as such.