Technology and Productivity Momentum
Dr. Aart de Geus, Chairman and Chief Executive Officer of Synopsys, analyses the relationship between technology and globalization, and reviews the factors driving Synopsys’ current focus on overall productivity throughout the design flow. Dr. de Geus also provides an overview of the recent product roadmap, highlighting the key technology advances within the Synopsys flow that are enabling productive design and verification. Part 1.
There is no question that the impact of technology combined with economics, or techonomics, is having a profound effect on many people’s lives. The electronics content in everyday products has increased dramatically over the past 40 years. From the earliest digital watch to the pocket calculator, and more recently with a whole raft of products supporting the wireless and network waves, the overall trend is clear. However, despite this historical evidence, predicting the exact nature of the next ‘killer app’ is always difficult – until of course it has happened.
Nevertheless, observing key trends can still provide a valuable insight into how the future will shape up. And understanding information about the marketplace, in the broadest sense, can help guide our strategic direction.
Convergence, Connectivity and Consumers
For twenty or thirty years, the underlying technology driver has been the power of computation, which is simply the amount of functionality that can be integrated on the IC and its clock speed. This was followed by a major wave in connectivity, and then more recently, in the past few years, the focus has centered on convergence. Today, consumer-centric products have completely converged with connectivity and computation.
If we consider these trends, the consumer has moved much more to the centre of gravity for electronic products. In fact, underlying this are some fairly fundamental changes that have occurred in the past ten years in the demographics of the global population, which we expect to continue. There has been a massive trend towards globalization. The importance of this cannot be overstressed. It is a phenomenon that is as significant as the industrialization that occurred in the late 1800s, or the new world discoveries made in the 1500s.
To better understand this phenomenon, we can look at globalization in terms of numbers. Focusing on the majority market for electronics products, which we’ll call the ‘middle class,’ we can see that the market size for the traditional Western world including Japan, South Korea and Taiwan has now effectively doubled with the addition of the middle classes of China, India, South America and parts of Eastern Europe. We have never before seen such a massive economic shift take place over such a short period of time – just twenty years or so.
Figure 1: Enormous Globalization – Middle Class Doubling
Although the market numbers are huge, there is a significant difference in median income and consequently spending power between the traditional middle class and the new markets. This globalization has had two profound effects on our industry. The first is to significantly increase semiconductor volume; the second is to massively increase pressure on price.
Semiconductor Cycles Continue
It’s widely known that the semiconductor industry has a tendency to cyclical behaviour over an 18-month to two-year period, which is primarily due to the issues of controlling supply and demand, and therefore price. The recessionary dips can be deep, 20 percent off the peak is typical. The industry did however suffer a much greater downturn, around 46 percent in 2001, which we did not see fully recover until 2004. My view is that this was no ordinary cyclical effect, but more of a re-structuring of the industry that took place. Further evidence of maturity within the industry is provided by the new reality of growth rates. Typically 17-20 percent during most of the 1980s and 90s, we are now seeing forecasts of 7-10 percent. Despite this major shift, this is still a strong industry that continues to grow through globalization.
Moore’s Law Has Continued Unabated
The process of adoption for new process nodes has followed a layering effect. However, we saw a distinct delay in the adoption of new technologies at 130nm. With the introduction of 130nm processes, new materials and techniques were introduced including copper and low-K dielectrics. The initial effect was to send a tremor through the industry because of the effects on lower yield, which took a year or 18-months to recover. Since then, 90nm processes have been adopted steadily and we’ve also seen the introduction of 65nm technology.
With new, smaller geometries there are some very significant technical challenges. These include managing signal integrity, dynamic and leakage power, as well as many manufacturing challenges involving lithography and yield optimization.
Summarizing the overall picture, today’s target consumer that we must keep in mind is essentially a teenager with limited spending power, but nevertheless the capability to purchase a lot of electronic equipment. This drives product development in a tremendous fashion, not only in price but in terms of time to market windows that have clearly shrunk significantly since 2001. In terms of the semiconductor cycle, the industry is now back to the levels first reached in the peak of 2001. Finally, of particular relevance to the design community is the fact that complexity on chips has continued to grow. The primary technology driver for the adoption of new process nodes has more to do with accommodating additional complexity and integration than higher speed. The key question today is whether more functionality can be added, and packaged, at minimum cost.
Figure 2: Characterising the Market Environment
Interdependency Rules Design
Designing for the latest process nodes presents an enormous number of technical challenges. With continued concern for quality-of-results, the area-speed trade-off, now power is on an equal footing. Balancing power with performance is a difficult task – in fact, just overcoming the new power challenges in isolation is extremely challenging.
Cost-of-results is something that we are increasingly confronted with. In the past, the way to reduce cost through increasing yield was to make the chip smaller, which shrinking process geometries have enabled. With the recent geometries below 130nm, attention to yield optimization is now a necessity. In other words, design and manufacturing, which used to be very independent, are now closely interrelated. Understanding the implications for these new interdependencies is crucial. One implication for Synopsys is how new tools can trade-off yield against the other success factors.
Time-to-results is the third key variable, which is usually the most tangible issue for the design team. Unfortunately the additional optimization required for the new variables means that we are less likely to predict and meet our project schedules.
Six Key Design Challenges
- Comprehensive verification is a difficult task and requires a systematic methodology. One way to do that is to re-use pre-verified IP blocks – though introducing buggy IP has proven fatal for many projects. Within verification the state space has grown much more rapidly than Moore’s law.
- Timing closure is still a central problem in implementation – that is where everything comes together. Of course, timing closure today cannot be viewed without simultaneously understanding signal integrity.
- Power, both dynamic heat dissipation and leakage power, is a problem especially at 90nm and 65nm geometries. These are phenomena that have grown dramatically in importance and for many chips are now the limiting factors in terms of what can be delivered to the customer.
- Photolithography has seen a dramatic rise in the technical challenges that are presented at the manufacturing level. Because the features we are designing today are smaller than the wavelength of light, it has been necessary to develop new photolithography techniques and tricks to address this.
- Yield is impacted by both manufacturing and design. Taking yield into account no longer means simply adhering to the process design rules as in the past, but is a feature that we must actively optimize for.
- Test ultimately brings us the measurability of our success, and must be considered very early in the design planning phase and carried through to post-manufacturing.
Taken individually, each of these design issues is sophisticated and challenging. What makes chip design so difficult is that these issues are completely interdependent today. What’s more, we expect this interdependency to grow over time. This is why design will remain a very sophisticated engineering science and at the same time a significant opportunity for product differentiation.
Towards Overall Productivity
Because of the increasing complexity and interdependence of design issues, we have seen a shift in the emphasis on the design flow towards overall success based on productivity through the entire flow. This has become the new optimization factor. Consequently, within Synopsys over the past two to three years, we have evolved our emphasis from sustaining technology leadership in each area to also providing productivity leadership across the overall design flow. This is a difficult objective to achieve and measure, but it is clear that looking at these problems independently is no longer sufficient, and so we have to find measures of overall productivity through the flow.
Using an automotive analogy, in the past we have excelled in the components business – we have produced the best engine, drive-chain, carburettor and so on. Now we must think in terms of the overall gas mileage, or miles per gallon we are delivering to our customers.
According to the design community, as reported in a 2005 EETimes survey, Synopsys continues to rank one in technology leadership today, will be number one in technology leadership in three years, and just as importantly, number one in terms of the level of technical support that we provide. This is a position that Synopsys has held since the first survey was run in 1997. We pay a great deal of attention to these results because we absolutely understand that the relationship between Synopsys and its customers is critical in enabling us to stay at the leading edge, and therefore to be able to effectively address overall productivity.
In Part 2: Dr. de Geus provides an overview of the recent product roadmap, highlighting the key technology advances within the Synopsys flow that are enabling continued advances in productive design and verification.
Aart de Geus
Chairman of the Board and Chief Executive Officer
Since co-founding Synopsys in 1986, Dr. Aart de Geus has expanded Synopsys from a start-up synthesis enterprise to a world leader in electronic design automation (EDA). As a technology visionary, he is frequently asked to speak on topics related to the electronics industry. As one of the leading experts on logic simulation and logic synthesis, Dr. de Geus was made a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) in January 1999. He was also honored for pioneering the commercial logic synthesis market by being named the third recipient ever to receive the IEEE Circuits and Systems Society Industrial Pioneer Award. In 2002, shortly after transacting the largest merger in EDA history, Dr. de Geus was named CEO of the Year by Electronic Business magazine; and in 2004, Entrepreneur of the Year in IT for Northern California by Ernst & Young. Dr. de Geus is active in the business community as a member of the board of the Silicon Valley Leadership Group (SVLG), the Electronic Design Automation Consortium (EDAC), and the Fabless Semiconductor Association (FSA). He is also heavily involved in education for the next generation, having created in 1999 the Synopsys Outreach Foundation, which promotes project-based science and math learning throughout Silicon Valley.
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