Diversifying Design Trends in North America
Semiconductor design activity in North America has diversified in response to shifting technical and economic drivers. John Koeter, Sr. Director of North America for Synopsys Professional Services, provides a Synopsys perspective on the design and semiconductor business trends in this region.
The Global Downturn
From 2001-2003, there was a downturn in semiconductor markets worldwide. Many veterans of the semiconductor industry argued – at the time – that the downturn was nothing new, that the semiconductor market has always been cyclical, and it is a function of supply and demand. However, we now know that the 2001-2003 downturn was twice as long and twice as deep as any other downturn in the history of high tech
Figure 1: Semiconductor Sales Cycle - Source: SIA, Synopsys
Of course, we are still recovering from the effects of this extraordinary semiconductor cycle. Like most dramatic economic events, the most recent downturn caused a shift in focus and a degree of restructuring in the semiconductor market.
Renewed Focus on Cost and Time to Market
One fundamental change in the semiconductor market is that consumer electronics has now overtaken the computer and communications segments to become the leading driver for semiconductor spending. This has led to a broad diversification of design starts in North America from computing and communications to consumer and as well as defense applications such as satellite imaging. The consequence of this for design is that cost and time to market have become even more critical success factors than before. While achieving high performance is also important, time-to-market and cost dominates at all stages of the design and manufacturing lifecycle. They are major considerations for chip development, prototyping, and manufacturing as well as software and end system costs such as upgradeability once the product is in the field.
The renewed focus on cost and time to market has not slowed down the race to finer geometries however. The propensity for leading-edge design at 90-nm and 65-nm is readily apparent in North America, though achieving volume production ramps has been significantly more challenging than previous process nodes due to, among other things, design-for-manufacturing issues. But this migration is now more strongly motivated by economic factors as well as the need for higher performance designs. The focus on time to results and cost of results also demands that companies be capital efficient and use proven solutions to address today’s challenging designs.
Globalization to Manage Costs
The 2001 downturn was so deep and long that many North American companies were forced into dramatic staff cuts. Design teams and CAD support personnel alike were affected. Many organizations have turned to a strategy of “globalization” to manage development costs as they rebuild their teams by taking advantage of the rapidly improving infrastructure and design talent in lower cost geographies. Emerging centers of design competence in Asia, especially within specific regions of India and China, are the primary beneficiaries. For many organizations, the offshore design satellites complement their North American design competencies. Design project tasks are now commonly partitioned across multiple time zones and continents.
Synopsys Professional Services has assisted companies in enabling global design in a number of ways. Using a common flow that is deployed worldwide has proven invaluable in assisting globally-distributed teams to work together. This is a proven solution and accelerates time to market while reducing support costs – especially important considering the reduced investment in in-house CAD support that many design organizations face. Flows and compatible sub-flows can be offered to customers as a way to jumpstart their design teams and become immediately productive when designing for 130-, 90- and 65-nm processes.
Synopsys Professional Services has also developed a secure, Internet-based design environment that enables global teams to collaborate 24x7 from anywhere in the world, sharing resources and expertise while utilizing a common design database. Apart from the engineer’s laptops, no local hardware is required as intensive synthesis, simulation, and physical design tasks can be run on remote compute farms, enabling efficient use of both hardware and software resources. A collaborative design infrastructure provides remote team members with security and revision control. Since designers log onto the compute farm, the data is not distributed and thus is secure.
Of course, these emerging geographies are more than a source of qualified labor for developers of chips and electronic systems; they represent significant growth opportunities as consumers of the developer’s products. Globalization gives companies based in North America an important presence in these promising markets.
The Growth of Fabless
The favorable financial case for utilizing foundries, as well as the pool of available design talent resulting from the electronics industry’s downsizing over the past several years, has led to a renewal in the design industry driven by fabless semiconductor companies. Sales from the fabless semiconductor market have grown at a compound annual growth rate (CAGR) of 25% from 1998 through 2004, compared to a 9% CAGR for the entire IC industry.
Figure 2: Fabless Companies IC Sales--Source: IC Insights
While evidence of the success of fabless semiconductor companies can be found worldwide, the North American region has especially embraced the model: in 2004, according to the Fabless Semiconductor Association, 76% of all fabless semiconductor revenue came from North America. Even some Integrated Device Manufacturers (IDMs) are employing a "fab-lite" model where a portion of their silicon manufacturing is outsourced to pure-play foundries.
Access to funding through a re-invigorated venture capital market has been an important factor in stimulating fabless start-up growth in the North American region during the last 24 to 36 months. However, the climate for funding is fundamentally different to that of pre-2001: scrutiny of the business case is now far more diligent, and the track record of company founders paramount. Fabless companies are attractive to venture investors because they are more capital-efficient, often outsourcing or offshoring not only manufacturing, but other non-critical functions as well.
The increase in the number of fabless semiconductor companies in North America has driven the need for greater physical design expertise – both in terms of people and design flows. Designing for 90-nm geometries and below demands a greater level of understanding and investment, especially in the back-end design process because issues such as timing, power and signal integrity closure become more challenging and interdependent.
For many fabless companies, whether to develop back-end design competence in-house, or to outsource it to a third-party, is a critical decision with far-reaching consequences. Success or failure of a chip can hinge on the physical implementation and for a start-up, this can be a "do or die" decision. Given the critical interdependence of front-end and back-end design and the complexity involved with integrating intellectual property (IP) blocks from various sources, many fabless companies recognize physical implementation competence as a critical success factor, and invest in the people and tools to undertake the back-end design in-house.
Synopsys Professional Services has responded to this issue by providing a comprehensive solution for physical design. This service enables design teams to address the immediate requirements for their design project through a flexible engagement model but also improves their capabilities and methods. As a result, many customers choose to tackle the back-end design collaboratively, with Synopsys experts and the company’s engineers working side-by-side. This model provides knowledge transfer alongside the establishment of the design flow so that the in-house team is able to develop a level of proficiency that will enable them to tackle subsequent projects.
The growth of the fabless semiconductor model has created a new type of vendor within the semiconductor ecosystem. The so-called “fabless ASIC” vendor has emerged to serve the needs of those companies that choose to innovate in algorithm and architecture design and outsource the rest of the design and manufacturing processes. These companies provide another choice to chip developers by acting as supply chain aggregators, taking a netlist or GDSII through implementation and managing the relationships with fab, assembly and test partners.
Implications for Design
While the North American market is more diversified than ever before, the renewed focus on cost and time to market continues to drive customers to advanced design at leading geometries with complex and interlinked design challenges. Design for yield, for example, is being deployed throughout the chip design process to ensure that silicon yield is optimized.
Closely related to manufacturing and yield, chip test has taken on new dimensions for many designers. As chip designs become larger and new process technologies require more complex failure modes, the length of scan chains and the number of scan patterns required have increased dramatically. To maintain adequate fault coverage, test application time and test data volume have also escalated, which has driven up the cost of test, often to unacceptable levels. Synopsys has invested in many innovative design-for-test solutions. For example, DFT Compiler MAX enables an enhanced Adaptive Scan architecture that offers a 10-50X reduction in test application time and test data volume, which helps to reduce the cost of test drastically.
Achieving efficient power closure in a design has become a primary requirement in ensuring high yielding, lower cost, manufacturable devices. At 90-nm and below, careful power planning and power management strategies in an ASIC are a requirement to ensure acceptable EM/IR drop. With supply voltages of 1V common, EM/IR drop should be limited to 50mV or less – achieving this is no trivial challenge across a large, complex die. Managing power through multi-VDD and multi-Vt methods among others also can lower the total device power, thus enabling a less expensive package or the removal of a heat sink.
Increases in chip complexity continue to drive the challenge of verifying ASICs. No longer can an engineer just simulate his design with 1s and 0s to find bugs, new technologies and methodologies are being applied. Coverage and assertions help ensure the design has been fully verified. Advanced testbenches with constrained random tests allow designers to generate more tests more quickly, getting chips fully verified sooner with higher quality accelerating time to market while reducing the risk of a costly respin. Synopsys’ Reference Verification Methodology provides the proven building blocks and methodology to attain functional coverage goals.
A Design-Based Future
While consolidating their EDA suppliers, North American chip developers continue to look for flexible but complete design solutions that solve their business problems, not just a single piece of the design process. Synopsys has responded with a broad but integrated portfolio of tools, IP, flows and design services that addresses the complete design process, enabling our customers to focus on their unique business competencies.
North America continues to support a business environment that incubates innovative ideas. The rich pool of design talent with leading-edge design experience and access to capital is probably unmatched anywhere else in the world, which is key to being able to realize innovative ideas in silicon. The adoption of the fabless manufacturing model that has been embraced and proven in this region provides a more level playing field for access to advanced manufacturing processes, and so seems set to continue to thrive. Combining these factors with the globalization of their workforces to better manage costs and identify emerging markets, North American chip companies can continue to compete and lead in the global semiconductor markets.
©2007 Synopsys, Inc. Synopsys and the Synopsys logo are registered trademarks of Synopsys, Inc. All other company and product names mentioned herein may be trademarks or registered trademarks of their respective owners and should be treated as such.