Design and Process Development for
65nm and Beyond
As process geometries continue to shrink, the distinction between design and manufacturing is becoming blurred. The clear demarcation that once existed between these steps is being replaced by the need for communication and collaboration between the two disciplines. Throwing the design ‘over the wall’ for production is a recipe for performance problems and low yield. Srini Raghvendra, Senior Director for DFM Solutions at Synopsys, and Terry Ma, Director of TCAD Product Marketing at Synopsys, describe the key needs for design and process development for 65nm and beyond.
Once process technology reached the 130nm mark, a new phenomenon became more pronounced as a result of the device geometries reaching the wavelength of light. Known as the ‘subwavelength gap’, the phenomenon caused distortions which were not considered by the traditional process rules that drive the design of ICs, photomask manufacturing, or photomask and wafer inspection.
Design for Manufacturing refers to a holistic approach between design and manufacturing. The key requirement is fast turnaround time for the manufacturing flow, from design to tapeout, and from tapeout to economic yield at production volumes. Synopsys’ approach has been to tighten the link between manufacturing data and the appropriate design implementation steps, such as place and route, with advanced tools such as Synopsys’ IC Compiler, part of the Galaxy™ Design Platform, which incorporates advanced DFM features. IC Compiler will be covered in greater depth in a future ‘Compiler’ article. However, the focus of this article is the post-layout DFM flow, covering the following key elements:
- Physical Verification
- Mask synthesis
- Lithography verification
- Mask qualification
- Mask data preparation
- TCAD – Technology Computer Aided Design
Apart from TCAD, the other tasks in the path to manufacturing follow a sequential process. TCAD may be used much earlier in the manufacturing flow when the process is in development, complementing silicon runs and providing preliminary SPICE models to the designers. TCAD also provides a mechanism for optimizing and controlling processes to improve parametric yield in manufacturing.
The overall goal with the flow from post-layout to manufacturing is to ensure that there are ‘no surprises’. If the design passes DRC and the chip timing is well understood, the transition from GDSII to silicon should not introduce any deviation in the behaviour of the device.
Mask Synthesis Solutions
One approach to overcome subwavelength gap problems is to pre-distort layout features during mask synthesis to compensate for the known patterning inaccuracies. In this way, the effective mask resolution can be improved by the application of Resolution Enhancement Techniques (RET) such as optical proximity correction (OPC), phase shift masks (PSM), and assist features (AF) without changing the design.
Synopsys’ mask synthesis engine, Proteus, applies optical proximity correction (OPC) to the mask data. This approach plays an increasingly critical role in enabling optical lithography to keep pace with shrinking chip dimensions. Proteus enhances silicon printability and enables the continued evolution toward ultra deep sub-micron designs by modifying layout geometries for systematic distortions introduced during fabrication. Extensive programmability ensures that Proteus can be adapted to accommodate virtually any type of optical proximity effect or other distortions arising from resist, etch and underlying topography influences.
Figure 1: Examples of optical proximity correction with Proteus
Accurately simulating complex diffraction patterns for a large chip design demands a significant amount of processing power. Additionally, as the process features shrink beyond 65nm, the volume of data associated with the chip increases significantly causing significant increase in turn around time (TAT) for mask manufacturing. Because of this, Proteus has been architected to solve this problem by the use of distributed processing (DP). The idea is simple – take the design, divide it into hundreds of pieces, then run each piece concurrently on a separate processor and combine the final results. While simple conceptually, implementing a software tool to be scalable to hundreds of processors is a complicated challenge.
Proteus OPC tool has been proven to run on more than 1,000 processors if necessary. While most OPC processing today requires tens, not thousands of processors, the ability to use more processors if necessary, means that TAT will not have to be a problem well into the 45nm node.
The need for more than one form of RET has become essential at the 65nm process. RET has also become a key differentiator for manufacturers. With the same equipment line, fabs can get different quality of results depending on the kind of RET they use and the ‘recipe’ for the RET. Proteus extensive scalability and programmability has been applied to support the application of Assist Features as well.
A recent customer evaluation of Assist Features on the contact layer for a 65nm process reduced the turnaround time for mask synthesis from 24 hours to 1 hour.
Modeling accuracy is another key requirement for the mask synthesis process, especially as technology geometries of 45nm and beyond are developed. The ability to customize and protect manufacturing process know-how/intellectual property in the RET area has become an important manufacturing issue. Since process engineers build different models for different process nodes, layers, and sometimes for regions of the same layer, it is critical for the user to be able to customize the model and the correction recipe in order to achieve the quality of results goal.
Phase-Shift Mask Application
Synopsys DFM tool suite also supports corrections for phase-shift mask (PSM) strategies, in particular alternating aperture phase shift mask (Alt-PSM). In Alt-PSM the two adjacent clear regions have respective phase shifts of 0 and 180 degrees. In the phase-shifting mask light diffracted into the nominally dark region between the clear regions interfere destructively at the edges of the pattern to create a sharper image on the wafer surface. This idea of selectively altering phase of the light passing through a photomask to take advantage of destructive interference to improve resolution and depth of focus. The improved image contrast leads to better resolution and depth of focus.
Synopsys' alternating aperture phase-shift mask (AA-PSM) technology provides manufacturability improvements through increased lithography resolution, a larger process window, and better performance.
Figure 2: Tighter CD uniformity with AA-PSM process vis-à-vis baseline process
Design engineers are motivated by higher product performance for the existing designs. However, this could be difficult without a major design change and associated process technology. For example, a product designed for 130nm can expect a major performance improvement after a design shrink (say, from 130nm to 90nm). Alt-PSM is a proven way to obtain the benefit of a ‘shrink’ without the redesign efforts that would otherwise be needed.
Synopsys’ AA-PSM technology has been used to fabricate transistors as small as 9nm using 248nm light source (see figure below).
Figure 3: SEM courtesy MIT Lincoln Laboratories; 9-nm gate length SOI transistor using 248nm lithography.
AA-PSM technology has been validated with production silicon since the 130nm node, and is the only commercially available strong phase-shifting technology currently used by several leading edge semiconductor companies in IC production.
Just as a design layout created by an automatic place and route tool needs DRC, a post mask synthesis layout also needs verification. The next primary step connecting design and manufacturing is to be able to verify the new post-RET GDSII vis-à-vis the manufacturing constraints – called ‘Lithography Verification’. Synopsys’ SiVL (silicon vs. Layout tool) addresses this link. SiVL compares a target design with its simulated silicon image to verify a design's manufacturability (see figure below). Going forward lithography verification will provide the key connection between the manufacturing and design worlds.
A lithography verification tool has two very important requirements - fast simulation and fast error classification and disposition. Fast simulation is needed so that designs with hundreds of millions of transistors can be simulated within a few hours using existing computing resources. SiVL achieves this, like Proteus OPC, through intelligent use of Distributed Processing (DP). The second requirement - fast error analysis and classification is achieved through a sophisticated user interface that has been custom built to focus the user directly to the kinds of errors that truly matter to the performance and yield of the design.
SiVL in Action (with Bridging Location – Metal Layer)
Within the domain of physical verification, accuracy is the primary requirement, closely followed by speed or turnaround time. Verification jobs that are not completed during an overnight run are an unacceptable hindrance to productivity. As the processing demands of physical verification have grown, largely due to having much larger designs (and volumes of data) to deal with, the processing speed must keep pace.
The other priority is debug. When a problem is highlighted by the physical verification process, the design teams must be able to understand the exact problem and the best way to fix it.
At 90nm and above, DRC is a very effective part of the verification process. In simple terms, if there’s a problem it’s down to two features being too close together, and the problem can be addressed by increasing the spacing. However, at 65nm and below, the rules have become a lot more complicated and there are more of them. Solving a problem may not be as simple as moving features further apart. This increased complexity at 65nm and below requires new approaches to reporting errors, and ways to fix them. These new techniques will include simulation-based DRC and lithography-compliance technology.
Both pure-play foundries and Integrated Device Manufacturers (IDMs) have to develop the design rules for their processes, and implement these within the chosen physical verification environment. Commonality between the use of verification engines in different parts of the flow, as well as the use of common languages and data formats within the DFM flow, can help users of this technology reduce their support and development costs.
Physical verification support for 65nm technologies is available today, with key products such as Hercules Physical Verification Suite (PVS) and SiVL® lithography rule checking. Synopsys is also well placed to meet the needs for physical verification of 45nm process technologies, with Hercules providing the common verification engine for SiVL and PSM.
Figure 5: Hercules: Common Physical Verification Engine
Hercules includes the features and programmability to handle complex 45nm Design Rule Checking (DRC) in a flexible, high-performance framework. High verification throughput is enabled with the ability to use distributed processing. Many design teams find that distribution of the verification job across 4-8 CPUs achieves an overnight turnaround. The scalability afforded by Hercules means that very large designs can be distributed across larger CPU clusters to achieve the required verification throughput. Hercules has demonstrated excellent performance in competitive benchmarks for both LVS and DRC.
Device extraction is another significant strength for Hercules technology, which assists in the development of new processes. The ability to capture all of the required data for the development of new SPICE models, including “Well Proximity” data and diffusion length, enables designers to understand how the geometries in a drawn device translate to real performance in silicon. The excellent programmability and flexibility of the Hercules engine means that it can be easily adapted to new process requirements to allow measurement of the parameters that are critical to device simulation.
One of the latest enhancements to Synopsys’ Hercules physical verification solution is a major improvement in the ability to find shorts after LVS. A new user interface includes a unique algorithm that allows connectivity to be re-evaluated on the fly. This means that when a designer examines the connectivity associated with a short, LVS does not have to be re-run every time a polygon is removed. This unique technology is a major benefit to the productivity associated with physical verification debug.
Technology CAD (TCAD)
TCAD, which precisely simulate advanced semiconductor processes and devices down to the atomic level, is traditionally used for exploring and optimizing process technologies and device characteristics throughout the technology development cycle. However, TCAD tools are a critical part of the overall DFM solution as it provides the bi-directional link between design and manufacturing, offering a predictive framework for correlating design parameter sensitivity with process variability. Cited in an EE Times article, “TSMC navigates dangerous channel to 65 nm,” dated May 2, 2005, Shang-Yi Chiang, Senior VP of R&D at TSMC emphasized that the challenges of manufacturing 65nm processes will have to be shared with the design team. Chiang said, "Process variations in such things as critical dimensions are becoming more and more difficult to control as process geometries shrink." The authors of the article believed that “it will be necessary for design teams to run technology-CAD models provided by their foundry partner.”
Aside from the traditional use of TCAD during process development, the increasing use of TCAD in manufacturing for advanced process control allows chip companies to attain target yield at the start of mass production and yet meet the time-to-market constraints. The alternative of sending the layout back to the design flow for some adjustment to solve any problems caused by process variability is potentially very time-consuming for each iteration required - especially at 65nm process node and beyond. For example, mobility enhancement through mechanical stress is being used as a way to increase device drive current. Device performance can be significantly improved by intentionally applying channel stresses in appropriate directions. However, process variability in manufacturing can alter the stress in the device channel, degrading device performance in some cases. Thus, design needs to account for manufacturing variations in a way that does not sacrifice the performance advantages provided by the new technology, whereas manufacturing needs to incorporate design constraints into the overall process control structure.
Another example of using TCAD for controlling the design sensitivity to process variability is a combination of feed-back and feed-forward controls in manufacturing. As depicted in the figures below, the feed-forward control can reduce the overall performance variation of a design due to the random statistical variations of individual process steps.
The methodology involves feeding in-line metrology data such as gate CD and gate oxide measurements into the TCAD physics-based Process Control Models (PCM) to determine the value of subsequent process parameters. For example, if the final gate CD is at the lower end of the specifications, with PCM the user can calculate the change in halo implant dose needed to keep the off-state leakage current within limits while simultaneously keeping the on currents in specification. It is also possible to distribute the change among several different process parameters such as dose, implant angle, anneal temperature, etc. The net result is an improvement in parametric product yield for specific designs without the manufacturing engineer having to understand the details of the design.
Synopsys’ unique TCAD solution include FLOOPS for process simulation and DESSIS for device modeling.
FLOOPS enables the entire process recipe such as diffusion, oxidation and implantation to be simulated in 2D and 3D – essentially all of those steps that comprise the manufacturing process. FLOOPS enables the modeling of 3D phenomenon such as stress and corner effects, which are inherent in nanoscale devices.
DESSIS supports a broad range of technologies including CMOS, SiGe, strained silicon, optoelectronics, power, compound semiconductor and SOI. Being able to assess different technology options is a significant benefit when exploring the possibilities to meet device performance goals.
The Genesis framework allows the management of simulation flow, visualization of simulation results, analysis of simulation data and generation of statistical information, providing insight into process characteristics and device performance which may not be attainable through measurements.
Comprehensive RTL-to-Mask DFM Solution
Synopsys DFM family is the solution of choice for yield-sensitive, high-value chips worldwide. Synopsys is committed to delivering technology and software products that help semiconductor companies accelerate their production yield ramps on advanced process nodes.
Synopsys' DFM product family is the solution-of-choice for 130nm yield-sensitive, high-value chips, worldwide. Eighty percent of all sub-180nm microprocessors, 50 percent of all sub-180nm DRAMs, 80 percent of all sub-180nm FPGA and graphics chips, and 75 percent of all sub-180nm cellular baseband chips produced use Proteus, and more than 80 percent of all photomasks produced use CATS.
About Srini Raghvendra
Srini Raghvendra is Senior Director for DFM Solutions at Synopsys. Srini joined Synopsys in 1989 and has held several senior positions in R&D, Marketing, and Corporate Business Development.
About Terry Ma
Terry Ma is Director of TCAD Product Marketing at Synopsys. Terry joined Synopsys in 2005, but has been involved in TCAD and process engineering since 1984.
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