SystemVerilog Testbench Automation
Open Standards Based Verification for VHDL, Verilog and Mixed-HDL Designs
Synopsys’ new SystemVerilog testbench automation tool, Pioneer-NTB, enables VHDL, Verilog or mixed-hardware design language (HDL) chip development teams to deploy advanced verification methodologies built on open standards. Tom Borgstrom, product line manager at Synopsys, introduces the Pioneer-NTB tool, and describes how it can make finding more bugs faster and easier regardless of the simulator or design language that’s used.
Increasing verification productivity remains one of the primary challenges for engineering teams tackling complex systems-on-chip (SoC) and silicon intellectual property (IP) design development. These teams know that as complexity increases the amount of effort needed for verification increases at an even faster rate, and that traditional verification techniques are often incapable of meeting tape-out schedule or quality targets. Fortunately, advanced coverage-driven, constrained-random, and assertion-based verification methodologies have been proven to increase verification productivity and quality, and are widely adopted by leading chip development teams. Accelerating this trend towards advanced verification methodologies is the emergence of EDA tools with support for SystemVerilog, which enable these techniques to be deployed using a widely-supported, open-standard language
Pioneer-NTB is a new SystemVerilog testbench automation tool from Synopsys that increases verification productivity and improves quality of complex SoC and IP designs by enabling engineers to use advanced coverage-driven, constrained-random and assertion-based verification techniques. It enables engineers to take advantage of Synopsys’ proven verification technology on third-party VHDL and Verilog simulators. Pioneer-NTB provides easy-to-use connections from its SystemVerilog verification environment to popular third-party simulators. By using Pioneer-NTB, verification engineers can adopt a single, standards-based, advanced verification infrastructure in mixed-simulation environments.
Pioneer-NTB is built on proven technology from VCS® and Vera® and takes advantage of the extensive VCS and Vera ecosystems including methodology, debug and analysis environments, assertion IP, and verification IP. Pioneer-NTB also provides extensive support for the OpenVera® hardware verification language (HVL), with up to 2x faster runtime performance compared to Vera.
SystemVerilog Testbench Automation
Standards-Based Verification for VHDL/Veriog Designs
Pioneer-NTB Supports Advanced Verification with SystemVerilog
SystemVerilog – the hardware description and verification language (HDVL) standard – is an evolutionary extension of the popular IEEE 1364-2001 Verilog language, and was developed by Accellera to dramatically improve productivity in the development of large-gate-count, IP-based, bus-intensive SoCs. SystemVerilog was derived from donations of proven technologies from vendors including Synopsys. SystemVerilog is targeted primarily at the chip implementation and verification flow, with powerful links to the system-level design flow.
SystemVerilog is scheduled to become the IEEE 1800 standard in 2005, after having been released by Accellera in 2004. Over 40 electronic design automation, IP and training service companies have already released or announced products and services supporting the language. Many leading design teams worldwide are using SystemVerilog in their design and verification projects today.
Pioneer-NTB provides extensive support for the SystemVerilog verification constructs used in advanced verification, including:
- Advanced Data Types
- Automatic Static Tasks & Functions
- Clocking Blocks
- Program Block
- Random Stimulus Generation
- Object-Oriented Programming (OOP)
- Associative Arrays
- Dynamic Arrays
- Threading & Synchronization
- Mailbox & Semaphores
- Virtual Interfaces
- DPI ‘C’ Interface
- Functional Coverage
Pioneer-NTB Supports the ARM-Synopsys Verification Methodology Manual for SystemVerilog
Deploying an advanced verification environment requires more than just tool support for SystemVerilog language features. A robust, proven methodology is essential in taking advantage of the power of SystemVerilog to create efficient and reusable verification environments.
ARM® and Synopsys have partnered to develop an open, reference methodology for verification with SystemVerilog. The result of this collaboration is now available as a book – Verification Methodology Manual (VMM) for SystemVerilog – with an associated verification library. The book documents years of expert know-how and industry best practices for architecting advanced, efficient verification environments using industry-standard SystemVerilog assertions, testbenches and functional coverage. It also provides developers with specifications for a library of verification functions to speed development and enable interoperable verification components. The VMM for SystemVerilog, peer-reviewed by over 30 verification engineers from leading semiconductor industry companies, helps enable chip development teams to achieve measurable functional coverage goals in less time with less effort, giving verification engineers and managers the confidence needed to tape out complex SoC and silicon IP designs.
Pioneer-NTB provides full support for the techniques described in the Verification Methodology Manual for SystemVerilog, as well as a pre-compiled version of the VMM Standard Library to help engineers deploy advanced verification environments faster. Source code for the VMM Standard Library is also available.
Verification Methodology Manual for SystemVerilog -- A Blueprint for SoC Verification Success with SystemVerilog
Pioneer-NTB Built on Proven Technology from Vera and VCS
Pioneer-NTB enables engineers to take advantage of Synopsys’ proven verification technology and ecosystem, even where third-party simulators are in use, by providing easy-to-use connections from its SystemVerilog verification environment to popular VHDL, Verilog and mixed-HDL simulators. This approach enables verification engineers to adopt a single, standards-based, advanced verification infrastructure in mixed-simulation and legacy environments.
Pioneer-NTB’s compilers and engines are built on Synopsys’ proven VCS and Vera technologies, including Synopsys Native Testbench (NTB), with support for IEEE 1800 SystemVerilog verification language constructs and the OpenVera® language. Engineers using Pioneer-NTB can quickly create highly-effective verification environments with object-oriented programming, advanced data types, constrained-random stimulus, functional coverage and assertions. Its unique architecture simultaneously optimizes testbench, functional coverage, assertions and verification IP into a single high-performance, native-compiled executable that runs with third-party simulators. Testbenches and assertions can be debugged with Pioneer-NTB’s intuitive graphical debug and analysis environment.
“We have had great success with Synopsys’ Native Testbench technology, and have taken advantage of its powerful constraint solver and coverage engines to develop sophisticated and powerful verification environments. Pioneer-NTB will be especially valuable to many of our major European clients, enabling them to take advantage of SystemVerilog verification with Synopsys’ Native Testbench technology running with their existing mixed-HDL simulation environments.”
Vice President of Consulting, Verilab
Assertion IP Library for Industry-Standard Protocols
Pioneer-NTB provides an assertion IP library to help verify complex protocols within the design. The assertion IP library allows designers to perform functional checks during simulation, identify and report protocol violations and capture assertion coverage data. Additionally, engineers will be able to use the library with Synopsys’ Magellan™ hybrid RTL formal analysis tool to prove complex design properties. Combined with the constrained-random stimulus generation and self-checking capabilities of the VCS Verification Library, the assertion IP library enables design teams to create comprehensive block-level and chip-level verification environments that comply with Synopsys’ RVM guidelines to increase design quality and lower development cost.
The assertion IP library includes the following interface and protocol standards: PCI®, AMBA™ 2 AHB and APB, 802.11a-g, AGP, and SMIA. Support for additional standards, including PCI X2.0®, PCI Express®, USB 2.0, DDR2, OCP 2.0, LPC, and CoreConnect™, is planned in future releases of Pioneer-NTB.
Pioneer-NTB Provided to Vera Customers
Pioneer-NTB provides extensive support for the OpenVera language, enabling Vera customers to easily migrate their existing environments to Pioneer-NTB and benefit from up to 2x faster runtime verification performance.
Pioneer-NTB and the Vera® testbench automation tool will be provided in a single package to current Vera and new Pioneer-NTB users, giving customers the flexibility to use either tool. Pioneer-NTB’s single-compiler, mixed-HVL capability will enable engineers to take advantage of existing OpenVera verification components in new SystemVerilog verification environments. This approach ensures that investment in existing infrastructure is preserved while adopting SystemVerilog.
Summary: Broadening Access to SystemVerilog for Verification
Pioneer-NTB delivers powerful, proven bug-finding verification technology and provides access to SystemVerilog for all engineers – regardless of the design language or simulator they are currently using. Pioneer-NTB fully supports the ARM-Synopsys Verification Methodology Manual for SystemVerilog, enabling IC development teams to adopt the same best practices as used by experts, resulting in more efficient and more thorough verification.
Pioneer-NTB demonstrates Synopsys’ commitment and lead in the delivery and support of standards-based verification solutions to the market, while support for existing design languages and simulators makes Pioneer-NTB easy to adopt and an efficient path to SystemVerilog.
Pioneer-NTB is in Limited Customer Availability (LCA) now; General Availability (GA) is expected in December 2005.
Tom Borgstrom is a product line manager at Synopsys, and is responsible for testbench automation products and verification methodology. Prior to joining Synopsys, Tom was vice president of marketing at TransEDA and has held senior sales and marketing roles at Exemplar Logic, Duet Technologies and CrossCheck Technology. Tom started his career as an ASIC design engineer with Matsushita in Osaka, Japan and has a BSEE and MSEE from The Ohio State University.
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