Designing for Yield: An Increasing Necessity
Attaining high yield for nanometer designs is a growing challenge. Every design decision and manufacturing process has a potential impact on yield. Design automation systems comprised of disparate tools cannot collectively address the causes of defects or effectively prevent yield loss. To be effective, design and manufacturing solutions must now treat the sources of defects systemically – offering yield loss prevention and recovery throughout the flow.
Defining Yield Loss and Defect Mechanisms
With the move to nanometer design, the semiconductor industry has seen an increase in defects and a decrease in target yield … resulting in reduced product margins and missed market windows. But what causes these nanometer defects and how can chip designers and manufacturers prevent them to minimize the ensuing yield loss?
Defects arise from such things as lithography errors, process variations, and environmental variations, and can contribute to functional and parametric yield loss (see Figure 1).
Figure 1: Defect and Yield Categories
Depending on the magnitude of the excursion from the nominal values, systematic and random defects can lead to either functional or parametric yield loss
Some defects contribute to functional yield loss. If a chip fails to run at all, it is counted as contributing to “functional yield loss”. Today, systematic variations are contributing to more than 60 percent functional yield loss at the 65nm node, as compared to less than five percent at the 350nm node. These are caused by spatial or pattern variations in the manufacturing process (such as metal width and thickness variations or mask misalignment). Random variations such as particle contamination that leads to short or open circuits also contribute to functional yield loss.
Other defects contribute to parametric yield loss. If a chip functions but does not meet its design specifications — perhaps because it is too fast, too slow, or too hot — it is counted as contributing to “parametric yield loss”. For example, subtle random variations during fabrication can contribute to threshold voltage problems, high leakage currents, interconnect parasitics … or impact the power consumption and operating temperature. Environmental variations may also contribute to parametric yield loss. Though chips with such defects can still function, they are unsuitable for their target application. The chips — though sometimes capable of being redeployed in a lower performance application — are counted as a “loss” because the target device cannot be delivered “right to market” (at the right time or cost … or with the right functionality).
Though defects are manifested during manufacturing, many of their effects can be prevented during implementation through the use of an effective design-for-yield solution.
Systemic Solution for Yield
A systemic solution that addresses yield throughout the semiconductor design flow – from process modeling to design implementation through mask synthesis – is now deemed essential.
- Such a systemic solution should provide (see Figure 2):
- TCAD (Technology Computer-Aided Design) software for predicting and optimizing process, device and interconnect characteristics through accurate and reliable simulation.
- A library development solution that supports advanced methodologies – such as sub-wavelength rules, foundry recommended rules, corners minimization – for creation of high-yield libraries.
- A Design for Yield (DFY) implementation solution that addresses power, timing, area, signal integrity, routability and yield concerns together, rather than independently.
- A comprehensive mask synthesis solution that deploys advanced Resolution Enhancement Techniques (RET) for manufacturability.
Figure 2: Systemic Solution Enables Design for Yield.
Preventing Functional Yield Loss
During logic and physical synthesis, incorporating yield-rated cells that are characterized for pertinent process technologies – and maybe even particular manufacturing lines – allows for yield optimization concurrent with the area, power, and timing goals. Library cells optimized for manufacturability minimize printability issues and reduce the mask synthesis effort.
Numerous routing optimization techniques can help improve functional yield. For example, minimizing critical areas for shorts and open circuits reduces the sensitivity of a design to random particle defects. The properly targeted use of wire-spreading and redundant Vias can also increase the robustness of the design to functional yield loss. Adding dummy metal fills with timing awareness can alleviate metal-line width and height variations arising from copper dishing and erosion, with minimal impact on the timing of critical paths (see Figure 3).
Figure 3: Concurrent Timing and Yield Closure.
Preventing Parametric Yield Loss
Variations during manufacturing can result in reduced performance and parametric yield loss. During corner analysis of inter-die (die-to-die) variation, all the circuit elements in a given die, lie either at the worst-case or best-case corner. However, in a deep-submicron technology, where intra-die (within a die) variations of circuit parameters are dominant, it is rare for all circuit elements to be at the same corner (worst or best). Additionally, most designs today support multiple modes of functionality (for example, many cell phones today are equipped with a chip for multimedia gaming, camera, and MP3 record-and-playback). To provide the worst case across all modes and corners, timing verification should be performed for multiple modes and multiple corners simultaneously (see Figure 4).
Figure 4: Multi-Corner, Multi-Mode Optimization.
The next step in timing analysis is the move to statistical analysis that will better model variations in the underlying silicon. Statistical timing analysis will become essential to analyze timing involving circuit parameter distribution and thereby identify the percentage of circuits that run at a given speed. Statistical timing analysis requires library cell models that describe how changes in various parameters affect the cell's delay. Parasitic extraction must also support variation of parameters.
Addressing Yield Loss
Addressing yield losses and identifying the root cause of failures is essential for yield loss recovery. Advanced fault models – such as bridging, transition and path delay – identify various defects that cause deep-submicron ICs to fail at-speed. An integrated flow between design implementation, test pattern generation and fault diagnostics aids in fast identification of defect mechanisms.
Aligning Mask Synthesis with Design
Lithography-compliant routing enables efficient mask synthesis such as optical proximity correction (OPC), and increases the yield while decreasing the turnaround time and implementation cost during mask synthesis. Effects that are avoided include low-contrast areas that lead to bridging, wire-length reductions that lead to poor Via overlap, or wire-width reductions that lead to "wire neckings" or opens.
Resolution enhancement techniques used in mask synthesis (after layout) improve printability and, hence, yield. These techniques include such things as OPC, the addition of assist features (AF) and the use of phase-shift masks (PSM). They need to be aligned with design implementation tools – in the sense that physical design must be “lithography compliant” – and will consider design information (intent, such as slack) to adjust, for example, the tolerances allowed for a given feature.
Understanding how a design influences yield is becoming an increasing necessity. In addition, lithography and manufacturing process knowledge is becoming more important in design to enable effective modeling of the yield loss. TCAD models are making their way into manufacturing, helping, for example, to simulate statistical variations of electrical parameters as a function of process parameters.
In summary, yield can no longer be considered an afterthought and it is now necessary to understand the impact of design decisions on yield. A systemic solution - from process modeling through IC design and mask synthesis - is required. Only with such a solution can yield be concurrently optimized with timing, area, power, signal integrity and routability.
Dr. Antun Domic joined Synopsys in April of 1997. In his current position, Dr. Domic manages the Implementation Group, responsible for Synopsys' flagship synthesis and physical design solutions, test automation, signal integrity, power analysis and timing and formal verification products. Dr. Domic holds a Ph.D. in Mathematics from the Massachusetts Institute of Technology and a B.S. in Mathematics and Electrical Engineering from the University of Chile.
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By Antun Domic
|"Particularly at 90-nm and below, all steps of design must optimize for yield concurrently with timing, area, power, signal integrity and routability."|