Compiler





Design Compiler 2005
Continued synthesis innovation delivers accurate prediction of post-layout timing with no need for wireload models (WLM). Neel Desai, product marketing manager, Synopsys RTL Synthesis, summarizes the key advances in the latest release of the industry-leading synthesis solution, driving further productivity enhancements for designers.

The Design Compiler® 2005 solution includes a new, innovative "topographical technology" enabling designers to accurately predict post-layout timing and area during RTL synthesis without the need for wireload model-based timing approximation. Created for RTL designers, the Design Compiler 2005 release requires no physical design expertise or changes to the synthesis use model. By accurately predicting post-layout timing, this solution eliminates costly iterations between synthesis and layout, providing faster time to results.

The "topographical technology" in Design Compiler 2005 utilizes Synopsys’ best-in-class placement and optimization technologies to drive accurate timing prediction within the synthesis engine, ensuring significantly better correlation to the final physical design. The Design Compiler 2005 solution increases RTL designers’ productivity by enabling them to focus on real design issues in the synthesis phase, and create a better starting point for physical implementation. Design Compiler 2005 shares technology with Synopsys’ Galaxy™ Design Platform physical design which reduces time-consuming iterations and improves time to results by driving a convergent RTL to GDSII flow.

Key Benefits
  • No need for wireload models (WLM)
  • Accurate prediction of post layout timing and area
  • No change to synthesis use model

Design Challenges are on the Rise
With growing design complexities, shrinking geometries, higher clock speeds and both power reduction and test compression requirements becoming mainstream design issues, timing and area correlation between synthesis and layout has become more challenging than ever. Larger synthesis block sizes along with shrinking geometries are driving net delays to be the dominant part of path delays. In earlier design generations, when the average block size was 10K to 50K gates, it was easier to predict net capacitances based on statistical information. The block sizes were small and the net lengths were relatively short. Hence it was easier to create wireload models with an estimated average net capacitance based on fan-out.

In today’s designs, synthesis block sizes are in the range of hundreds of thousands to millions of gates, which makes it much harder to estimate the net capacitances based on statistical information. This results in timing and area correlation issues where the results after RTL synthesis do not correlate to post-physical implementation results. The challenge is amplified even further, since place and route solutions cannot compensate for a poor start point handed off from synthesis.

Several approaches are used by designers to overcome this lack of correlation. One approach is to overly-constrain timing in synthesis. This pessimistic approach to synthesis results in increased area post layout. Another possibility is to use optimistic, or zero WLM in synthesis, which causes even worse correlation and can lead to increased iterations between synthesis and physical implementation. Both methods result in suboptimal designs, reduced designer productivity and longer time to results.

Design Compiler 2005 – The Latest Innovation in Synthesis
Design Compiler 2005 is the latest innovation in synthesis, delivering accurate correlation to post-layout timing and area without the need for wireload models. It is designed for RTL designers and requires no physical design expertise or changes to the synthesis use model.

The accurate prediction of layout timing and area in Design Compiler 2005 is achieved through the innovative "topographical technology." It enables RTL designers to fix real design issues while still in synthesis and generate a better start point for physical design, eliminating costly iterations. This significantly boosts RTL designers’ productivity. Design Compiler 2005 shares technology with Synopsys Galaxy™ Design Platform physical design ensuring a smooth, convergent path from RTL to GDSII.

Topographical Technology
Topographical technology in Design Compiler 2005 is a break-through innovation that utilizes Synopsys’ best-in-class placement and optimization technologies to drive accurate timing prediction within the RTL synthesis engine, and ensures correlation to physical design. It drives synthesis with virtual layout-based timing which eliminates the need for users to provide WLM for synthesis. With the knowledge of actual design topography, Design Compiler 2005’s "topographical technology" accurately predicts net capacitances and continuously updates their values as the synthesis process progresses.

Figure 1
Figure 1: Topographical technology in Design Compiler 2005 is the latest innovation in RTL synthesis

As an integral part of Design Compiler 2005, topographical technology drives synthesis with accuracy for all design objectives including timing, area, power and test. With "topographical technology," RTL designers can focus on the real design issues while still in the synthesis phase, thereby achieving higher productivity.

Topographical technology requires no physical expertise or change to the current synthesis use model. In addition, it shares technology with Synopsys’ physical implementation solution ensuring a convergent, smooth flow from RTL to GDSII.

No Need for Wireload Models
Design Compiler 2005 removes the dependency of synthesis on WLMs completely. The "topographical technology" in Design Compiler 2005 accurately predicts net capacitances based on the topography of the design, hence accommodates for the variation of net capacitances in the design. This eliminates the need for over-constraining the design or the use of optimistic WLM in synthesis.

The accurate prediction of net capacitances in Design Compiler 2005 drives synthesis to produce a netlist that is optimized for all design objectives including area, timing, test, and power. The final netlist is ready for physical implementation.

Figure 2 compares the net capacitance based on WLM and net capacitances with topographical technology plotted against the actual layout capacitance. Data points on the orange line would indicate an exact prediction of net capacitance value; the further the data point is from this line, the more inaccurate the prediction.

Figure 2
Figure 2: Net capacitance values based on WLMs and Design Compiler 2005

The Design Compiler 2005 plot clearly shows that with "topographical technology," the predicted net capacitance values are far superior to the net capacitance predicted with WLM.

Accurate Prediction of Post Layout Timing and Area
Accurate prediction of post layout timing and area in synthesis is key to RTL designer productivity. It enables the identification and fixing of real design issues while still in synthesis, and the creation of a superior start point for physical design. It also reduces costly iterations between synthesis and layout and achieves better quality of results, faster.

Figure 3 shows timing and area correlation between synthesis results using Design Compiler 2005 and physical implementation results over many designs. A data point on the orange line would mean exact correlation. As shown in the figure, Design Compiler 2005 timing and area results correlate very well with post physical implementation results.

Figure 3
Figure 3: Design Compiler 2005 provides better correlation to post-layout timing and area.

No Change to Synthesis Use Model
Design Compiler 2005 is designed for RTL designers and does not require any changes to the current synthesis use model. It is a single command option that requires no physical expertise or data and shares the same physical library with Synopsys’ Galaxy Design Platform’s physical design solution.

As shown in Figure 4, the inputs to Design Compiler 2005 are the same as before, with the exception of physical library (pdb):

  • Design RTL
  • Logical Library (db), Liberty (without a need for WLM)
  • Physical Library (pdb)
  • Design constraints (sdc)

The output is a netlist optimized for timing, area, test and power with accurately predicted layout timing, ready for physical implementation handoff.

Figure 4
Figure 4: Design Compiler 2005 inputs and outputs

Design Compiler 2005 significantly boosts RTL designers’ productivity with the new topographical technology. It concurrently optimizes for all design objectives, including area, timing, power and test with accurate virtual layout based timing. By accurately predicting post- layout timing, the new Design Compiler 2005, as part of the Galaxy™ Design Platform, eliminates costly iterations between synthesis and layout. Once again, Synopsys is driving the evolution of RTL synthesis by delivering higher designer productivity and faster time to results.

About Neel Desai
Neel Desai is product marketing manager for RTL Synthesis at Synopsys.

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©2007 Synopsys, Inc. Synopsys and the Synopsys logo are registered trademarks of Synopsys, Inc. All other company and product names mentioned herein may be trademarks or registered trademarks of their respective owners and should be treated as such.

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By Neel Desai, product marketing manager, Synopsys RTL Synthesis

WEB LINKS
 -Design Compiler

"Without requiring wireload models, timing results were within 4 percent of post layout timing, which represents a 9x improvement in correlation."
IDT

"…timing prediction was within 1 percent of post layout timing without requiring any physical information."
SGI

"…With the Design Compiler 2005 release we have seen a 4x improvement in timing and area correlation."
ARM