Compiler






Designing Using the AMBA 3 AXI Protocol
   Easing the Design Challenges and Putting
   the Verification Task on a Fast Track to
   Success

The need for higher-performance applications is driving the requirement for a new age of on-chip communication infrastructure. Increasing the clock frequency no longer addresses this higher performance requirement, as the bottleneck is inherent in the existing bus infrastructure.

This article examines the advantages of the new AMBA™ 3 AXI™ protocol for on-chip bus infrastructure, and how it revolutionizes the future of high-performance SoC interconnect. It describes the AMBA 3 AXI protocol feature set that makes it suitable for the new high-performance, low-latency and low-power designs. It also examines the verification tools and IP necessary to successfully complete design and verification in today’s reduced development cycle.

The Ever-Shrinking Development Cycle
As design complexity continues to increase, time-to-market pressures force shorter and shorter development cycles. High-performance designs are technically complex and require vast amounts of verification to ensure correct operation. Interconnect topologies with multiple address, data, handshaking buses and transaction cycles that complete out of order over many cycles enable high performance and low latency, but can no longer be verified with traditional directed-testing methodologies.

These features on their own not only take the verification task to the next level of complexity, but also introduce corner cases that must be captured and tested. Unfortunately these corner cases are typically very hard to identify and, if missed, could mean failure of the resulting design.

Standards and Reuse
One way to reduce the risk and pressures of a new design is through the use of standards and reuse. Today, designers can also choose from a range of open specifications of on-chip interface protocols. Choosing this option facilitates use of proven, pre-designed, pre-verified IP and verification components. With more proven IP in the design, and by the deployment of verification IP (VIP), designers can focus on differentiating their design rather than verification of the standard protocol.

Use of existing standard protocol IP and VIP shortens subsystem creation time, as less effort and time is required to build and verify the SoC infrastructure. The use of these standards protocols also aids interoperability, as all components will have been designed to the same specification. This dramatically reduces the overall risk associated with the design.

The AMBA 3 protocol family defines a new set of on-chip interface protocols for SoC designs. These are the latest generation protocols, which are interoperable with existing bus technology defined in the AMBA 2 Specification. The AMBA 3 AXI protocol is an advanced microprocessor system bus interface that is part of this new protocol family. It is targeted at high-performance, high-frequency system designs and includes a number of features that make it suitable for a high-speed, submicron interconnect

AMBA 3 AXI Protocol: A Powerful Evolution
The new AMBA 3 AXI (Advanced eXtensible Interface) protocol builds on the many benefits of the AMBA 2 standard by greatly extending the performance and flexibility of the systems based on AMBA technology. Based on the industry’s needs, and created in collaboration with more than 30 companies, the AMBA 3 AXI protocol is available now and addresses the needs of the coming generation of designs.

The AMBA 3 AXI protocol defines a unidirectional channel architecture, which enables the efficient use of register slices to pipeline the connection for higher speeds, or to enable the use of multiple clock domains for low power. The support of multiple outstanding transactions and out-of-order transaction completion, together with the efficient use of the read, write and address/control channels, enables systems to achieve levels of performance and efficiency limited only by the capabilities of the peripherals themselves.

One of the key goals of the AMBA 3 AXI protocol is interoperability with the existing AMBA technology. A clear advantage of this interoperability is that designers have access to a wide array of silicon-proven IP and VIP for AMBA protocols, increasing options for reuse and further increasing the time designers spend on design differentiation rather than general subsystem creation and validation.

AMBA 3 AXI Protocol: Channel Power
The AMBA 3 AXI architecture differs significantly from previous AMBA protocols by the introduction of channels. Each of the five independent channels consists of a set of information signals and uses a two-way VALID and READY handshake mechanism. The information source uses the VALID signal to show when valid data or control information is available on the channel. The destination uses the READY signal to show when it can accept the data. Both the read data channel and the write data channel also include a LAST signal to indicate when the transfer of the final data item within a transaction takes place. Read and write transactions each have their own address channels. The appropriate address channel carries all of the required address and control information for a transaction.

The read data channel conveys both the read data and any read response information from the slave back to the master. The read data channel includes the data bus, which can be 8, 16, 32, 64, 128, 256, 512, or 1024 bits wide, and a read response indicating the completion status of the read transaction.

The write data channel conveys the write data from the master to the slave. The Write data channel includes the data bus, which can be 8, 16, 32, 64, 128, 256, 512, or 1024 bits wide, and one byte lane strobe for every eight data bits, which indicates which bytes of the data bus are valid.

AMBA 2 AHB versus AMBA 3 AXI Efficiency Comparison
Figures 1 and 2 show the bus cycles for the AMBA 2 AHB and AMBA 3 AXI protocols, respectively. In Figure 1, a burst with multiple data requires multiple addresses, all data must be transmitted in the same order as the addresses, and multiple data must be contiguous. These restrictions reflect the requirements of the AMBA 2 AHB specification.

Figure 1
Figure 1: Cycles for the AMBA 2 AHB Protocol

Figure 2 shows the increased efficiency of the AMBA 3 AXI protocol. Only one address is needed for a burst, data can be transmitted decoupled from the address and even out of order, and data associated with different addresses can be interleaved.

Figure 3
Figure 2: Cycles for the AMBA 3 AXI Protocol

Deployment of a Layered Constrained-Random Verification Methodology
Verification for complex chips is challenging; the problem is even worse when designing to a new protocol. In addition to design application testing, significant effort is needed to learn the new protocol to make use of the features the protocol brings to the design. The huge set of complicated verification tasks is driving designers to become smarter about verification, including the tools and techniques they use.

Directed testing no longer generates enough coverage in the time allotted, so other approaches are required. Deployment of a layered verification methodology, when combined with the use of constrained-random verification techniques, is required to meet the challenge of verifying a subsystem that uses the AMBA 3 AXI protocol. A directed testing methodology simply cannot create enough system stimuli to reach the required coverage goals in the shortened development cycle.

The Synopsys Reference Verification Methodology (RVM) is one example of a reusable, layered verification methodology that employs constrained-random techniques to achieve full coverage in the shortest possible time and effort.

Leveraging Verification IP and Assertion IP
A new interface such as the AMBA 3 AXI protocol requires additional verification to ensure that the protocol has been implemented correctly and to ensure that none of the included components violates the protocol standard. This requires the generation of verified stimuli, responses, and some sort of monitor to check that all transactions adhere to the protocol standard.

One solution would be to create a handcrafted protocol transactor to generate the desired stimuli. While this option seems “free” to the engineer, there are many frequently overlooked costs of taking this approach. Example costs such as the time it takes to create this transactor, ensuring adherence to the protocol, supporting it throughout the development cycle, and designing it for reuse in subsequent projects all have to be considered. Of course, the actual transactor will require its own verification environment to ensure some level of accuracy. Finally, this hand-crafted verification block will need to support a layered methodology with the generation of constrained-random transactions if it is really going to help with the verification task.

A better approach to take is to use verification IP from a reliable vendor, such as Synopsys, which has done the hard work to verify the accuracy of the generated protocol and implemented the required interfaces to enable the use of the layered methodology with constrained-random transaction generation.

The Synopsys DesignWare® master and slave VIP for the AMBA 3 AXI protocol can be used to generate and respond to transactions that stress the interconnection of design blocks. The Synopsys monitor for the AMBA 3 AXI protocol is used to verify the bus protocol and generate bus coverage and crossport coverage information, and has the required hooks to support a self-checking scoreboard-based testbench. Figure 3 shows the effect of using VIP to enable a constrained-random verification approach.

Figure 3
Figure 3: Constrained-Random Methodology and VIP Address Time-to-Market Pressures

Assertion IP should also be included at this stage to enable the use of formal property verification tools, such as the Synopsys Magellan™ hybrid formal tool, to further speed up the verification task. Both the VIP and the assertion IP should be included in the verification environment. The VIP provides the advanced simulation features such as cross-port coverage and scoreboard Constrained-Random Methodology notification. The assertion IP can be used as the golden reference and enable the use of formal tools and techniques.

Leveraging Existing IP
One of the advantages of the AMBA 3 AXI protocol is that it can support existing subsystems that use AMBA 2 protocols. In the embedded core market, the most widely-adopted on-chip bus is the AMBA 2 AHB protocol.

Backward compatibility with AMBA 2 protocols is a major feature of the AMBA 3 AXI protocol, making a wide variety of intellectual property (IP) available for reuse. Bridges from the AMBA 3 AXI protocol to the AMBA 2 protocols are available to enable reuse of existing IP. Figure 4 shows an example of bridging, using a mix of DesignWare (DW) IP and VIP.

Figure 4
Figure 4: Bridging from the AMBA 3 AXI protocol to AMBA 2 protocols to enable reuse

This simple bridging enables existing IP and subsystems to be reused, which will help shorten the development cycle even more since interface redesign is not required. Even whole subsystems can be reused by taking advantage of the efficient memory interface that the AMBA 3 AXI protocol enables.

There is an enormous existing base of IP components and tools available for the AMBA 2 protocols, such as the offerings from Synopsys that are delivered as part of the DesignWare Library. Both synthesizable IP and verification IP are included in the royalty-free library, including peripherals such as DMA Controller, Interrupt Controller, and UART.

Verification IP supporting the RVM layered methodology and constrained-random verification techniques are also available from Synopsys for the AMBA 2 protocols. Reusing subsystems based on AMBA 2 technology and IP with the AMBA 3 AXI protocol interfaces eases the transition to the new specification. Since the legacy IP blocks have been preverified, more time again can be spent on design and verification of the new subsystem components and application.

Summary
The AMBA 3 AXI protocol is a well supported interface with very powerful features to address the needs of next generation designs. Coupling the power of this new protocol with the ability to utilize existing design and verification IP provides a wide ranging set of design options. Powerful verification IP, tools, and methodologies such as RVM available from Synopsys and the Synopsys DesignWare Library further allow designers to focus on the portions of their design that are unique and differentiated.

These tools and methodologies add significant value and reduce the overall development cycle when designing the next generation of products using AMBA technology.

Mick Posner, Synopsys
Mick Posner joined Synopsys in 1994 and is currently Product Manager for Synopsys’ DesignWare Library. Before that, he was an application consultant and technical marketing manager at Synopsys. He holds a Bachelors Degree in Electronic and Computer Engineering from the University of Brighton, England.

Darrin Mossor, Synopsys
Darrin Mossor joined Synopsys in 1989 and is currently a Staff CAE responsible for DesignWare verification IP for the AMBA 2 and AMBA 3buses. During his years at Synopsys, Mr. Mossor has also managed the DesignWare Memory Models group and managed local resources as well as a development team in India.

Before coming to Synopsys, Mr. Mossor worked at Eagle Design Automation as a development engineer and at Model Technology as a technical marketing and development engineer. He holds a BSEE from Gonzaga University.

This article was first published in the June issue of Synopsys’ Verification Avenue.

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©2007 Synopsys, Inc. Synopsys and the Synopsys logo are registered trademarks of Synopsys, Inc. All other company and product names mentioned herein may be trademarks or registered trademarks of their respective owners and should be treated as such.

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